公开(公告)号：US20230397419A1

公开(公告)日：2023-12-07

申请号：US17816651

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Wesley O. Mckinsey ,  John Hopkins

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556

Abstract: For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.

公开(公告)号：US20240130132A1

公开(公告)日：2024-04-18

申请号：US18391442

申请日：2023-12-20

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anikumar Chandolu ,  Wesley O. Mckinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/20

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/20

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

公开(公告)号：US20240105510A1

公开(公告)日：2024-03-28

申请号：US17950640

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Wesley O. Mckinsey

IPC: H01L21/768 ,  H01L21/3215 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76886 ,  H01L21/32155 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/53271 ,  H01L23/535

Abstract: Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.

公开(公告)号：US20220310632A1

公开(公告)日：2022-09-29

申请号：US17806829

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. Mckinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11524 ,  H01L27/11556

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.