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    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SEMICONDUCTOR DEVICES AND STRUCTURES
    2.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SEMICONDUCTOR DEVICES AND STRUCTURES 有权
    形成半导体器件结构和相关半导体器件和结构的方法

    公开(公告)号：US20140374811A1

    公开(公告)日：2014-12-25

    申请号：US13921509

    申请日：2013-06-19

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

    IPC: H01L21/308 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L29/42324 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/788

    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control region.

    Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和在控制区域下具有基本对准侧壁和电荷结构的封盖区域。

    MEMORY ARRAYS WITH AIR GAPS BETWEEN CONDUCTORS AND THE FORMATION THEREOF
    3.
    发明申请
    MEMORY ARRAYS WITH AIR GAPS BETWEEN CONDUCTORS AND THE FORMATION THEREOF 审中-公开
    存储器阵列与导体之间的空气压力及其形成

    公开(公告)号：US20140159132A1

    公开(公告)日：2014-06-12

    申请号：US13706532

    申请日：2012-12-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David A. Daycock ,  Matthew J. King ,  Christopher J. Larsen

    IPC: H01L29/51 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4991

    Abstract: Memory arrays and their formation are disclosed. The formation of one such memory array includes forming first and second spacers respectively adjacent to sidewalls of first and second conductors so that the first and second spacers extend into an opening between the first and second conductors and terminate above bottoms of the first and second conductors, and closing the opening with a material that extends between the first and second spacers so that an air gap is formed in the closed opening.

    Abstract translation: 公开了存储器阵列及其形成。 一个这样的存储器阵列的形成包括分别与第一和第二导体的侧壁相邻地形成第一和第二间隔物，使得第一和第二间隔物延伸到第一和第二导体之间的开口中并终止在第一和第二导体的底部之上， 并且用在第一和第二间隔件之间延伸的材料封闭开口，使得在封闭的开口中形成气隙。

    Memory array with an air gap between memory cells and the formation thereof
    4.
    发明授权
    Memory array with an air gap between memory cells and the formation thereof 有权
    存储器阵列与存储单元之间的空气间隙及其形成

    公开(公告)号：US08716084B2

    公开(公告)日：2014-05-06

    申请号：US13902052

    申请日：2013-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Andrew Bicksler ,  Christopher J. Larsen

    IPC: H01L21/336 ,  H01L29/66

    CPC classification number: H01L29/66825 ,  H01L21/764 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66833

    Abstract: A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor.

    Abstract translation: 形成存储器阵列的方法包括在半导体上形成电介质，在电介质上形成电荷存储结构，通过电介质和电荷存储结构形成隔离区并延伸到半导体中，使隔离区凹陷到 电平低于电介质的上表面的电平并且在半导体的上表面的水平以上，在电荷存储结构和凹陷隔离区域上形成存取线，并且在凹陷隔离件上形成气隙 区域，使得气隙通过电荷存储结构，使得气隙延伸到并终止于进入管线的底表面，并且使得整个气隙位于进入管线的底表面和 半导体的上表面。

    Methods of forming microelectronic devices
    5.
    发明授权
    Methods of forming microelectronic devices 有权

    公开(公告)号：US12127401B2

    公开(公告)日：2024-10-22

    申请号：US18321659

    申请日：2023-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  Lifang Xu

    IPC: H10B41/27 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/76877 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H10B43/27

    Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

    METHODS OF FORMING MICROELECTRONIC DEVICES
    7.
    发明公开
    METHODS OF FORMING MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20230301081A1

    公开(公告)日：2023-09-21

    申请号：US18321659

    申请日：2023-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  Lifang Xu

    IPC: H10B41/27 ,  H01L21/768 ,  H01L23/538 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L21/76877 ,  H01L23/5384 ,  H01L23/5386 ,  G11C5/06 ,  H01L23/5381 ,  H10B43/27

    Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

    Semiconductor device structures with liners
    8.
    发明授权
    Semiconductor device structures with liners 有权

    公开(公告)号：US11355607B2

    公开(公告)日：2022-06-07

    申请号：US14875493

    申请日：2015-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

    IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L21/308 ,  H01L27/11517 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11558 ,  H01L29/06 ,  H01L21/02

    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING LINERS
    10.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING LINERS 有权

    公开(公告)号：US20250159944A1

    公开(公告)日：2025-05-15

    申请号：US19022308

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

    IPC: H10D30/68 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  H10B41/00 ,  H10B41/30 ,  H10B41/60 ,  H10D62/10 ,  H10D64/01

    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

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