公开(公告)号：US09385278B2

公开(公告)日：2016-07-05

申请号：US14617423

申请日：2015-02-09

Applicant: Micron Technology, Inc.

Inventor： Xiaolong Fang ,  Lifang Xu ,  Tingkai Li ,  Thomas Gehrke

IPC: H01L33/32 ,  H01L33/48 ,  H01L21/66 ,  H01L23/544 ,  H01L33/00 ,  H01L21/78

CPC classification number: H01L33/32 ,  H01L21/78 ,  H01L22/10 ,  H01L22/32 ,  H01L22/34 ,  H01L23/544 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

公开(公告)号：US20130309858A1

公开(公告)日：2013-11-21

申请号：US13948050

申请日：2013-07-22

Applicant: Micron Technology, Inc.

Inventor： Farrell Good ,  Baosuo Zhou ,  Xiaolong Fang ,  Fatma Arzum Simsek-Ege

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/302

CPC classification number: H01L21/768 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract translation: 形成多个间隔特征的方法包括在下面的材料上形成牺牲性硬掩模材料。 牺牲硬掩模材料具有至少两层不同的组成。 去除部分牺牲硬掩模材料以在下面的材料上形成掩模。 掩模的各个特征具有至少两层不同的组成，其中每个单独特征的层之一具有至少400.0MPa的拉伸内应力。 单个特征具有大于0.0MPa的总拉伸内在应力。 当蚀刻到下面的材料中时，使用掩模以形成包括下面的材料的多个间隔的特征。 公开了其他实现。

公开(公告)号：US20150155440A1

公开(公告)日：2015-06-04

申请号：US14617423

申请日：2015-02-09

Applicant: Micron Technology, Inc.

Inventor： Xiaolong Fang ,  Lifang Xu ,  Tingkai Li ,  Thomas Gehrke

IPC: H01L33/32 ,  H01L33/00 ,  H01L21/66

CPC classification number: H01L33/32 ,  H01L21/78 ,  H01L22/10 ,  H01L22/32 ,  H01L22/34 ,  H01L23/544 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

Abstract translation: 公开了半导体生长衬底和用于芯片分离的相关系统和方法。 用于制造半导体器件的代表性方法包括在位于衬底材料的相邻器件生长区域之间的切割街道上形成间隔开的结构。 该方法还可以包括通过将半导体材料的第一部分添加到器件生长区域并将半导体材料的第二部分添加到该结构体来外延生长半导体材料。 该方法还可以进一步包括在器件生长区域处形成半导体器件，并且在切割街道处通过在切割街道处去除间隔开的结构和下面的衬底材料来将半导体器件彼此分离。

公开(公告)号：US08980752B2

公开(公告)日：2015-03-17

申请号：US13948050

申请日：2013-07-22

Applicant: Micron Technology, Inc.

Inventor： Farrell Good ,  Baosuo Zhou ,  Xiaolong Fang ,  Fatma Arzum Simsek-Ege

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/302

CPC classification number: H01L21/768 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract translation: 形成多个间隔特征的方法包括在下面的材料上形成牺牲性硬掩模材料。 牺牲硬掩模材料具有至少两层不同的组成。 去除部分牺牲硬掩模材料以在下面的材料上形成掩模。 掩模的各个特征具有至少两层不同的组成，其中每个单独特征的层之一具有至少400.0MPa的拉伸内应力。 单个特征具有大于0.0MPa的总拉伸内在应力。 当蚀刻到下面的材料中时，使用掩模以形成包括下面的材料的多个间隔的特征。 公开了其他实现。