中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.014 seconds)

    GROUND CONNECTION FOR SEMICONDUCTOR DEVICE ASSEMBLY
    2.
    发明申请
    GROUND CONNECTION FOR SEMICONDUCTOR DEVICE ASSEMBLY 有权

    公开(公告)号：US20210175182A1

    公开(公告)日：2021-06-10

    申请号：US16706443

    申请日：2019-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Jong Sik Paek ,  Youngik Kwon ,  Yeongbeom Ko

    IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

    Abstract: Semiconductor device assemblies with improved ground connections, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly may include one or more semiconductor dies mounted on an upper surface of a package substrate. Further, the package substrate includes a bond pad disposed on the upper surface, which may be designated as a ground node for the semiconductor device assembly. The bond pad may be electrically connected to an electromagnetic interference (EMI) shield of the semiconductor device assembly through a conductive component attached to the bond pad and configured to be in contact with the EMI shield at a sidewall surface or a top surface of the semiconductor device assembly, thereby forming the ground connection. Such ground connection may reduce a processing time to form the EMI shield while improving yield and reliability performance of the semiconductor device assemblies.

    Semiconductor devices with package-level compartmental shielding and associated systems and methods
    3.
    发明授权
    Semiconductor devices with package-level compartmental shielding and associated systems and methods 有权

    公开(公告)号：US11515174B2

    公开(公告)日：2022-11-29

    申请号：US16681214

    申请日：2019-11-12

    Applicant: Micron Technology, Inc.

    Inventor： Youngik Kwon ,  Jong Sik Paek

    IPC: H01L21/56 ,  H01L23/31 ,  H01L21/67 ,  H01L23/552

    Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.

    Stacked semiconductor dies for semiconductor device assemblies
    4.
    发明授权
    Stacked semiconductor dies for semiconductor device assemblies 有权

    公开(公告)号：US11362071B2

    公开(公告)日：2022-06-14

    申请号：US17001435

    申请日：2020-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56

    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

    STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES
    6.
    发明申请
    STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES 有权

    公开(公告)号：US20220271013A1

    公开(公告)日：2022-08-25

    申请号：US17741799

    申请日：2022-05-11

    Applicant: Micron Technology, Inc.

    Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56

    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

    STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES
    8.
    发明公开
    STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230290684A1

    公开(公告)日：2023-09-14

    申请号：US17690981

    申请日：2022-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Wei Chang Wong ,  Radhakrishna Kotti ,  Raj K. Bansal ,  Youngik Kwon ,  Po Chih Yang ,  Venkateswarlu Bhavanasi

    IPC: H01L21/78 ,  H01L23/58

    CPC classification number: H01L21/78 ,  H01L23/585 ,  H01L27/108

    Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.

    SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL COMPARTMENTAL SHIELDING AND ASSOCIATED SYSTEMS AND METHODS
    9.
    发明申请
    SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL COMPARTMENTAL SHIELDING AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20230041760A1

    公开(公告)日：2023-02-09

    申请号：US17969620

    申请日：2022-10-19

    Applicant: Micron Technology, Inc.

    Inventor： Youngik Kwon ,  Jong Sik Paek

    IPC: H01L21/56 ,  H01L23/31 ,  H01L21/67 ,  H01L23/552

    Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.

    STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES
    10.
    发明申请
    STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES 有权

    公开(公告)号：US20220059500A1

    公开(公告)日：2022-02-24

    申请号：US17001435

    申请日：2020-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31

    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

Patent Agency Ranking