公开(公告)号：US07404139B2

公开(公告)日：2008-07-22

申请号：US11040861

申请日：2005-01-21

申请人： Mohit K. Prasad ,  Nitin Vig ,  Arnab K. Mitra ,  Amrit P. Singh ,  Gaurav Davra

发明人： Mohit K. Prasad ,  Nitin Vig ,  Arnab K. Mitra ,  Amrit P. Singh ,  Gaurav Davra

IPC分类号： H03M13/03

CPC分类号： H03M13/4169 ,  H03M13/3961 ,  H03M13/6502

摘要： A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

摘要翻译： 对编码的数据符号序列进行解码的最大似然序列估计（MLSE）解码器包括用于计算编码序列的每个网格级的分支度量的分支度量单位，用于使用所述编码序列计算每个网格级的路径度量的路径度量单位 计算的分支度量，以及M-at-time追溯单元，用于使用所计算的路径度量来执行M-at-time追溯操作。 M-at-time追溯操作在单次M-at-time追溯操作中生成M个解码的数据符号。

公开(公告)号：US07231586B2

公开(公告)日：2007-06-12

申请号：US10896268

申请日：2004-07-21

申请人： Mohit K. Prasad ,  Gaurav Davra ,  Arnab K. Mitra ,  Amrit P. Singh ,  Nitin Vig

发明人： Mohit K. Prasad ,  Gaurav Davra ,  Arnab K. Mitra ,  Amrit P. Singh ,  Nitin Vig

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6505

摘要： A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.

摘要翻译： 一种用于对先前使用一个或多个唯一码字多项式进行编码的数据符号序列的方法和系统，其中至少一个唯一码字多项式被多次使用。 使用唯一的码字多项式来计算一组2 D-1 唯一分支度量，其中d是唯一码字多项式的数量。 所计算的2个独立分支度量的集合被存储在存储器中。 然后，基于存储的2个独立分支度量的集合来计算路径度量。 基于所计算的路径度量来生成解码数据符号序列。

公开(公告)号：US20060168502A1

公开(公告)日：2006-07-27

申请号：US11040861

申请日：2005-01-21

申请人： Mohit Prasad ,  Nitin Vig ,  Arnab Mitra ,  Amrit Singh ,  Gaurav Davra

发明人： Mohit Prasad ,  Nitin Vig ,  Arnab Mitra ,  Amrit Singh ,  Gaurav Davra

IPC分类号： H03M13/03

CPC分类号： H03M13/4169 ,  H03M13/3961 ,  H03M13/6502

摘要： A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

摘要翻译： 对编码的数据符号序列进行解码的最大似然序列估计（MLSE）解码器包括用于计算编码序列的每个网格级的分支度量的分支度量单位，用于使用所述编码序列计算每个网格级的路径度量的路径度量单位 计算的分支度量，以及M-at-time追溯单元，用于使用所计算的路径度量来执行M-at-time追溯操作。 M-at-time追溯操作在单次M-at-time追溯操作中生成M个解码的数据符号。

公开(公告)号：US08390354B2

公开(公告)日：2013-03-05

申请号：US11435917

申请日：2006-05-17

申请人： Nitin Vig ,  Arnab K. Mitra

发明人： Nitin Vig ,  Arnab K. Mitra

IPC分类号： H03K3/289

CPC分类号： H03K3/356156 ,  H03K3/356173

摘要： A device and associated method to reduce hold-time violations are disclosed. The device includes a latch module with a selectable delay. The latch module includes a control input to select the delay through the latch. In one embodiment, the delay of the latch is the time between when a latching edge of a clock signal is experienced by the latch until data changes at the output of the latch. In the event of a hold-time violation at latches that are downstream of other latches, a longer delay can be selected at an upstream latch to provide a slower delay path for data provided to the downstream latch violating the hold-time. By providing a slower delay path, the data being latched at the downstream latch will not change as quickly after a latching signal is received, and therefore the possibility of a hold-time violation is reduced.

摘要翻译： 公开了一种减少持续时间违规的设备和相关方法。 该装置包括具有可选延迟的锁存模块。 闩锁模块包括用于选择通过闩锁的延迟的控制输入。 在一个实施例中，锁存器的延迟是当锁存器经历时钟信号的锁存边沿直到在锁存器的输出处的数据变化之前的时间。 在其他锁存器下游的锁存器处的保持时间违规的情况下，可以在上游锁存器处选择更长的延迟，以向提供给下游锁存器的数据提供较慢的延迟路径，从而违反保持时间。 通过提供较慢的延迟路径，在接收到锁存信号之后，被锁存在下游锁存器处的数据将不会快速变化，因此减少了保持时间违规的可能性。

公开(公告)号：US07421610B2

公开(公告)日：2008-09-02

申请号：US11370381

申请日：2006-03-06

申请人： Arnab K. Mitra ,  Amrit Singh ,  Nitin Vig

发明人： Arnab K. Mitra ,  Amrit Singh ,  Nitin Vig

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12

CPC分类号： G06F1/04 ,  G01R31/31727

摘要： A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.

摘要翻译： 用于诸如SOC的集成电路器件的时钟产生电路增加了测试覆盖。 时钟发生电路包括在其时钟输入端接收输入时钟信号的第一和第二锁存器和分别在第一和第二数据输入端接收输入时钟信号和作为分频时钟的第二锁存电路的输出的选择器 信号。 逻辑门具有连接到第一锁存器的输出端的第一输入端和接收扫描模式信号的第二输入端。 逻辑门产生提供给选择器的选择器控制信号。

公开(公告)号：US20070268053A1

公开(公告)日：2007-11-22

申请号：US11435917

申请日：2006-05-17

申请人： Nitin Vig ,  Arnab K. Mitra

发明人： Nitin Vig ,  Arnab K. Mitra

IPC分类号： H03K3/289

CPC分类号： H03K3/356156 ,  H03K3/356173

摘要： A device and associated method to reduce hold-time violations are disclosed. The device includes a latch module with a selectable delay. The latch module includes a control input to select the delay through the latch. In one embodiment, the delay of the latch is the time between when a latching edge of a clock signal is experienced by the latch until data changes at the output of the latch. In the event of a hold-time violation at latches that are downstream of other latches, a longer delay can be selected at an upstream latch to provide a slower delay path for data provided to the downstream latch violating the hold-time. By providing a slower delay path, the data being latched at the downstream latch will not change as quickly after a latching signal is received, and therefore the possibility of a hold-time violation is reduced.

摘要翻译： 公开了一种减少持续时间违规的设备和相关方法。 该装置包括具有可选延迟的锁存模块。 闩锁模块包括用于选择通过闩锁的延迟的控制输入。 在一个实施例中，锁存器的延迟是当锁存器经历时钟信号的锁存边沿直到在锁存器的输出处的数据变化之前的时间。 在其他锁存器下游的锁存器处的保持时间违规的情况下，可以在上游锁存器处选择更长的延迟，以向提供给下游锁存器的数据提供较慢的延迟路径，从而违反保持时间。 通过提供较慢的延迟路径，在接收到锁存信号之后，被锁存在下游锁存器处的数据将不会快速变化，因此减少了保持时间违规的可能性。

公开(公告)号：US20070201586A1

公开(公告)日：2007-08-30

申请号：US11743157

申请日：2007-05-02

申请人： Mohit Prasad ,  Gaurav Davra ,  Arnab Mitra ,  Amrit Singh ,  Nitin Vig

发明人： Mohit Prasad ,  Gaurav Davra ,  Arnab Mitra ,  Amrit Singh ,  Nitin Vig

IPC分类号： H03D1/00 ,  H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6505

摘要： A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.

摘要翻译： 一种用于对先前使用一个或多个唯一码字多项式进行编码的数据符号序列的方法和系统，其中至少一个唯一码字多项式被多次使用。 使用唯一的码字多项式来计算一组2 D-1 唯一分支度量，其中d是唯一码字多项式的数量。 所计算的2个独立分支度量的集合被存储在存储器中。 然后，基于存储的2个独立分支度量的集合来计算路径度量。 基于所计算的路径度量来生成解码数据符号序列。

公开(公告)号：US20060020875A1

公开(公告)日：2006-01-26

申请号：US10896268

申请日：2004-07-21

申请人： Mohit Prasad ,  Gaurav Davra ,  Arnab Mitra ,  Amrit Singh ,  Nitin Vig

发明人： Mohit Prasad ,  Gaurav Davra ,  Arnab Mitra ,  Amrit Singh ,  Nitin Vig

IPC分类号： H03M13/00

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6505

摘要： A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.

摘要翻译： 一种用于对先前使用一个或多个唯一码字多项式进行编码的数据符号序列的方法和系统，其中至少一个唯一码字多项式被多次使用。 使用唯一的码字多项式来计算一组2 D-1 唯一分支度量，其中d是唯一码字多项式的数量。 所计算的2个独立分支度量的集合被存储在存储器中。 然后，基于存储的2个独立分支度量的集合来计算路径度量。 基于所计算的路径度量来生成解码数据符号序列。

公开(公告)号：US20070022312A1

公开(公告)日：2007-01-25

申请号：US11370381

申请日：2006-03-06

申请人： Arnab Mitra ,  Amrit Singh ,  Nitin Vig

发明人： Arnab Mitra ,  Amrit Singh ,  Nitin Vig

IPC分类号： G06F1/06

CPC分类号： G06F1/04 ,  G01R31/31727

摘要： A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.

摘要翻译： 用于诸如SOC的集成电路器件的时钟产生电路增加了测试覆盖。 时钟发生电路包括在其时钟输入端接收输入时钟信号的第一和第二锁存器和分别在第一和第二数据输入端接收输入时钟信号和作为分频时钟的第二锁存电路的输出的选择器 信号。 逻辑门具有连接到第一锁存器的输出端的第一输入端和接收扫描模式信号的第二输入端。 逻辑门产生提供给选择器的选择器控制信号。

公开(公告)号：US07151396B2

公开(公告)日：2006-12-19

申请号：US11098106

申请日：2005-04-04

申请人： Nitin Vig ,  Amab K. Mitra

发明人： Nitin Vig ,  Amab K. Mitra

IPC分类号： H03H11/26

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K2005/0013 ,  H03K2005/00156 ,  H03K2005/00247

摘要： A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.