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Patent Agency Ranking
公开(公告)号：US09705516B1
公开(公告)日：2017-07-11
申请号：US15224296
申请日：2016-07-29
Applicant: Movellus Circuits, Inc.
Inventor： Jeffrey Alan Fredenburg , Muhammad Faisal , David Michael Moore
CPC classification number: H03L7/0995 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03L7/0998
Abstract: A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit.
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公开(公告)号：US10158365B2
公开(公告)日：2018-12-18
申请号：US15224224
申请日：2016-07-29
Applicant: Movellus Circuits, Inc.
Inventor： Muhammad Faisal , Jeffrey Alan Fredenburg
IPC: H03L7/099 , H03L7/081 , H03L7/08 , H04L27/152
Abstract: A reconfigurable frequency and delay generator is disclosed, and a representative embodiment may include a phase sampler and plurality of configurable oscillator stages, each configurable oscillator stage of the plurality of configurable oscillator stages comprising: a plurality of core inverters coupled in series, a last core inverter of the plurality of core inverters generating an output signal having a configurable output frequency; and a plurality of delay control circuits, each delay control circuit of the plurality of delay control circuits coupled to an output of a corresponding core inverter of the plurality of core inverters.
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公开(公告)号：US09762249B1
公开(公告)日：2017-09-12
申请号：US15224199
申请日：2016-07-29
Applicant: Movellus Circuits, Inc.
Inventor： Muhammad Faisal , Jeffrey Alan Fredenburg , David Michael Moore
CPC classification number: H03L7/07 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B2201/011 , H03L7/093 , H03L7/099 , H03L7/0998 , H03L7/18 , H03L2207/50 , H03M7/16
Abstract: A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.
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公开(公告)号：US09680480B1
公开(公告)日：2017-06-13
申请号：US15224280
申请日：2016-07-29
Applicant: Movellus Circuits, Inc.
Inventor： Jeffrey Alan Fredenburg , Muhammad Faisal , David Michael Moore
CPC classification number: H03M7/16 , H03L7/0814 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/22
Abstract: A reconfigurable digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator to generate an input signal having a reference frequency. A representative embodiment of the reconfigurable digital phase-locked loop integrated circuit may include a first digital phase-locked loop circuit configured to generate a first signal having a first frequency which is an integer multiple of the reference frequency; and a second digital phase-locked loop circuit coupled to the first digital phase-locked loop, the second digital phase-locked loop configured to generate a second, output signal having a second output frequency in response to a plurality of configuration parameters, the second frequency having a configurable fractional offset from the integer multiple of the reference frequency, and to match a phase of the second output signal with a first signal phase.
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公开(公告)号：US20180034468A1
公开(公告)日：2018-02-01
申请号：US15224224
申请日：2016-07-29
Applicant: Movellus Circuits, Inc.
Inventor： Muhammad Faisal , Jeffrey Alan Fredenburg
IPC: H03L7/099 , H03L7/08 , H04L27/152 , H03L7/081
CPC classification number: H03L7/0997 , H03L7/0802 , H03L7/081 , H03L7/0996 , H03L7/0998 , H03L2207/50 , H04L27/0014 , H04L27/152
Abstract: A reconfigurable frequency and delay generator is disclosed, and a representative embodiment may include a phase sampler and plurality of configurable oscillator stages, each configurable oscillator stage of the plurality of configurable oscillator stages comprising: a plurality of core inverters coupled in series, a last core inverter of the plurality of core inverters generating an output signal having a configurable output frequency; and a plurality of delay control circuits, each delay control circuit of the plurality of delay control circuits coupled to an output of a corresponding core inverter of the plurality of core inverters.
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