公开(公告)号：US20240047395A1

公开(公告)日：2024-02-08

申请号：US17818003

申请日：2022-08-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Sheng-Fu HUANG ,  Shing-Yih SHIH

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/08 ,  H01L25/0657 ,  H01L24/05 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/05687 ,  H01L2224/0236 ,  H01L2224/0235 ,  H01L2224/08146 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/024

摘要： A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.

公开(公告)号：US20220005758A1

公开(公告)日：2022-01-06

申请号：US16919078

申请日：2020-07-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Sheng-Fu HUANG ,  Shing-Yih SHIH

IPC分类号： H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/48

摘要： A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.

公开(公告)号：US20210175116A1

公开(公告)日：2021-06-10

申请号：US16707177

申请日：2019-12-09

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/535

摘要： The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor device structure includes a conductive structure disposed over a semiconductor substrate, and a conductive plug disposed over the conductive structure. The conductive plug is electrically connected to the conductive structure. The semiconductor device structure also includes a first spacer formed on a sidewall surface of the conductive plug, and an etch stop layer disposed over the semiconductor substrate. The etch stop layer adjoins the first spacer. The semiconductor device further includes a first inter-layer dielectric (ILD) layer disposed over the etch stop layer and next to the conductive plug, wherein the first ILD layer is separated from the first spacer by an air gap.

公开(公告)号：US20210098461A1

公开(公告)日：2021-04-01

申请号：US16583288

申请日：2019-09-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH ,  Tse-Yao HUANG

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L23/528

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.

公开(公告)号：US20210020455A1

公开(公告)日：2021-01-21

申请号：US16514986

申请日：2019-07-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L21/48 ,  H01L23/29 ,  H01L23/538

摘要： A conductive via structure includes a first dielectric layer, a conductive pad, a second dielectric layer, and a redistribution layer. The conductive pad is in the first dielectric layer. The second dielectric layer is disposed above the first dielectric layer and has an opening. The conductive pad is in the opening. The opening has a first width at a top surface of the second dielectric layer and a second width at a bottom surface of the second dielectric layer. A difference between the first width and the second width is in a range from about 1.5 um to about 3 um. The redistribution layer extends from the top surface of the second dielectric layer to the conductive pad.

公开(公告)号：US20200168615A1

公开(公告)日：2020-05-28

申请号：US16215098

申请日：2018-12-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L27/108

摘要： The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A substrate including a conductive layer formed thereon is provided. The conductive layer is patterned to form a plurality of conductive patterns extending along a first direction. A cap layer is conformally formed to cover the plurality of conductive patterns. A patterned hard mask is formed over the cap layer. The plurality of conductive patterns are etched through the patterned hard mask to form a plurality of conductive islands. In some embodiments, the plurality of conductive islands are separated from each other by a plurality of first gaps along the first direction. In some embodiments, the plurality of conductive islands are separated from each other by the cap layer and a plurality of second gaps along a second direction that is different from the first direction.

公开(公告)号：US20200168457A1

公开(公告)日：2020-05-28

申请号：US16244885

申请日：2019-01-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH ,  Yu-Mei NI ,  Shih-Yi LIU

IPC分类号： H01L21/033 ,  G03F1/38 ,  G03F7/20

摘要： A method of manufacturing a semiconductor structure includes providing a substrate and a photoresist over the substrate; placing a mask over the photoresist; exposing the photoresist to a predetermined electromagnetic radiation through the mask; and removing at least a portion of the photoresist exposed to the predetermined electromagnetic radiation. The mask includes a first portion configured to totally allow the predetermined electromagnetic radiation passing through, a second portion configured to partially allow the predetermined electromagnetic radiation passing through, and a third portion configured to block the predetermined electromagnetic radiation, the second portion is disposed between the first portion and the third portion.

公开(公告)号：US20230377885A1

公开(公告)日：2023-11-23

申请号：US17664218

申请日：2022-05-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L21/027 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/0273 ,  H01L21/02016 ,  H01L21/02697 ,  H01L21/76897

摘要： A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.

公开(公告)号：US20210305223A1

公开(公告)日：2021-09-30

申请号：US16833690

申请日：2020-03-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00

摘要： A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

公开(公告)号：US20210287937A1

公开(公告)日：2021-09-16

申请号：US16820267

申请日：2020-03-16

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/306 ,  H01L21/027 ,  H01L23/00

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. The second semiconductor structure is positioned on the first connecting structure and includes two second conductive features positioned on the two first conductive layers. The first conductive layer has a first width, the second conductive feature has a second width greater than the first width, and the different width forms a step-shaped cross-sectional profile near an interface of the first conductive layer and the second conductive feature.