公开(公告)号：US11482293B2

公开(公告)日：2022-10-25

申请号：US17363020

申请日：2021-06-30

Applicant: NOVATEK Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Yong-Ren Fang ,  Yi-Chuan Liu ,  Yi-Yang Tsai ,  Po-Hsiang Fang

IPC: G11C19/28 ,  G09G3/20

Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.

公开(公告)号：US20190113939A1

公开(公告)日：2019-04-18

申请号：US16052654

申请日：2018-08-02

Applicant: Novatek Microelectronics Corp.

Inventor： Yong-Ren Fang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: G05F1/46 ,  H03K5/24 ,  G01R19/165

CPC classification number: G05F1/46 ,  G01R19/16528 ,  H03K5/24

Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

公开(公告)号：US11974371B2

公开(公告)日：2024-04-30

申请号：US17388748

申请日：2021-07-29

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Wang ,  Che-Wei Yeh ,  Keko-Chun Liang ,  Yong-Ren Fang ,  Yi-Chuan Liu

IPC: H05B45/33 ,  G09G3/32

CPC classification number: H05B45/33 ,  G09G3/32

Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.

公开(公告)号：US11509296B2

公开(公告)日：2022-11-22

申请号：US17239671

申请日：2021-04-25

Applicant: NOVATEK Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Yi-Chuan Liu

IPC: H03K5/156 ,  G06F1/06 ,  H03K5/133 ,  H03K5/00 ,  H03K5/135

Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

公开(公告)号：US20220343833A1

公开(公告)日：2022-10-27

申请号：US17238179

申请日：2021-04-22

Applicant: NOVATEK Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Yong-Ren Fang ,  Yi-Chuan Liu

IPC: G09G3/32

Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

公开(公告)号：US10256967B2

公开(公告)日：2019-04-09

申请号：US15863983

申请日：2018-01-08

Applicant: Novatek Microelectronics Corp.

Inventor： Chang-Cheng Huang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/093 ,  H03L7/089

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

公开(公告)号：US11367390B2

公开(公告)日：2022-06-21

申请号：US16429049

申请日：2019-06-02

Applicant: Novatek Microelectronics Corp.

Inventor： Keko-Chun Liang ,  Yu-Hsiang Wang ,  Jhih-Siou Cheng ,  Yi-Chuan Liu ,  Ju-Lin Huang

IPC: G09G3/3233 ,  G09G3/3275

Abstract: A display apparatus and a method for noise reduction are introduced. The method comprises steps of sensing a first pixel signal being superimposed by noises from a first pixel through a first sensing line in a first phase of a sensing operation and sensing a first noise signal from the first sensing line in a second phase of the sensing operation. The method further comprises steps of sensing a second noise signal from a second sensing line in the first phase of the sensing operation, and sensing a third noise signal from the second sensing line in the second phase of the sensing operation. The method further removes the noises that are superimposed to the first pixel signal according to a difference between the first pixel signal and the first noise signal and a difference between the second noise signal and the third noise signal to generate a denoised sensing value of the first pixel.

公开(公告)号：US20220006608A1

公开(公告)日：2022-01-06

申请号：US17163527

申请日：2021-01-31

Applicant: NOVATEK Microelectronics Corp.

Inventor： Yong-Ren Fang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/027

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals

公开(公告)号：US20210383749A1

公开(公告)日：2021-12-09

申请号：US17409824

申请日：2021-08-24

Applicant: Novatek Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Po-Hsiang Fang ,  Ju-Lin Huang

IPC: G09G3/32

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

公开(公告)号：US11010136B2

公开(公告)日：2021-05-18

申请号：US16159734

申请日：2018-10-15

Applicant: Novatek Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang

IPC: G06F7/58 ,  H03M3/00 ,  H03K3/84

Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.