公开(公告)号：US20240014324A1

公开(公告)日：2024-01-11

申请号：US17810846

申请日：2022-07-06

Applicant: NXP B.V.

Inventor： Viet Thanh Dinh ,  Asanga H. Perera ,  Arjan Mels

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/7856 ,  H01L29/66803 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/845

Abstract: A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.

公开(公告)号：US20160351699A1

公开(公告)日：2016-12-01

申请号：US14721648

申请日：2015-05-26

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Arjan Mels

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/783 ,  H01L21/761 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7823

Abstract: A field-effect transistor (FET) includes, a first drain, a second drain, a body and a gate region. The gate region has a length, and is configured and arranged to create, in response to a gate voltage, a channel that is in the body, between the first and second drains, and along the length of the gate region. A plurality of body dropdowns are located in the gate region and are spaced along a width of the gate region. Each of the body dropdowns are configured and arranged to provide an electrical contact to the body for biasing purposes.

Abstract translation: 场效应晶体管（FET）包括第一漏极，第二漏极，主体和栅极区域。 栅极区域具有长度，并且被配置和布置成响应于栅极电压而产生在主体中，在第一和第二漏极之间以及沿着栅极区域的长度的沟道。 多个主体下拉位于栅极区域中并且沿着栅极区域的宽度间隔开。 每个身体下拉装置被构造和布置成为身体提供用于偏压目的的电接触。

公开(公告)号：US10218171B2

公开(公告)日：2019-02-26

申请号：US15344552

申请日：2016-11-06

Applicant: NXP B.V.

Inventor： Dongyong Zhu ,  Arjan Mels ,  Peter Christiaans

IPC: H02H9/02 ,  H02H9/04 ,  H01L27/02

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

公开(公告)号：US20170373490A1

公开(公告)日：2017-12-28

申请号：US15344552

申请日：2016-11-06

Applicant: NXP B.V.

Inventor： DONGYONG ZHU ,  Arjan Mels ,  Peter Christiaans

IPC: H02H9/02 ,  H01L27/02 ,  H02H9/04

CPC classification number: H02H9/025 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0285 ,  H01L27/0288 ,  H02H9/046

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.