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公开(公告)号：US11784651B2
公开(公告)日：2023-10-10
申请号：US17512231
申请日：2021-10-27
Applicant: NXP B.V.
Inventor： Ravichandar Reddy Geetla , Deependra Kumar Jain , Gaurav Agrawal , Ravi Kumar
CPC classification number: H03L7/0992 , H03L7/0814 , H03L7/0995 , H03L7/1974 , H03M3/30
Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.
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Patent Agency Ranking
公开(公告)号：US20230126891A1
公开(公告)日：2023-04-27
申请号：US17512231
申请日：2021-10-27
Applicant: NXP B.V.
Inventor： Ravichandar Reddy Geetla , Deependra Kumar Jain , Gaurav Agrawal , Ravi Kumar
Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.
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公开(公告)号：US12191859B2
公开(公告)日：2025-01-07
申请号：US18332042
申请日：2023-06-09
Applicant: NXP B.V.
Inventor： Saurabh Goyal , Divya Tripathi , Krishna Thakur , Deependra Kumar Jain
Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
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公开(公告)号：US11601130B2
公开(公告)日：2023-03-07
申请号：US17304628
申请日：2021-06-23
Applicant: NXP B.V.
Inventor： Gaurav Agrawal , Deependra Kumar Jain , Krishna Thakur
Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.
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公开(公告)号：US20240204757A1
公开(公告)日：2024-06-20
申请号：US18332042
申请日：2023-06-09
Applicant: NXP B.V.
Inventor： Saurabh Goyal , Divya Tripathi , Krishna Thakur , Deependra Kumar Jain
CPC classification number: H03K3/017 , H03K3/0315 , H03K5/135
Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
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公开(公告)号：US20220416796A1
公开(公告)日：2022-12-29
申请号：US17304628
申请日：2021-06-23
Applicant: NXP B.V.
Inventor： Gaurav Agrawal , Deependra Kumar Jain , Krishna Thakur
Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.
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