公开(公告)号：US20240204086A1

公开(公告)日：2024-06-20

申请号：US18067322

申请日：2022-12-16

Applicant: NXP B.V.

Inventor： Jay Paul John ,  James Albert Kirchgessner ,  Johannes Josephus Theodorus Marinus Donkers ,  Ljubo Radic

IPC: H01L29/737 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66242

Abstract: A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.

公开(公告)号：US20240030308A1

公开(公告)日：2024-01-25

申请号：US17813504

申请日：2022-07-19

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Johannes Josephus Theodorus Marinus Donkers ,  Bernhard Grote

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/10

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  H01L29/7375 ,  H01L29/1004

Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.

公开(公告)号：US20250098189A1

公开(公告)日：2025-03-20

申请号：US18824976

申请日：2024-09-05

Applicant: NXP B.V.

Inventor： Jay Paul John ,  James Albert Kirchgessner ,  Johannes Josephus Theodorus Marinus Donkers ,  Ljubo Radic ,  Patrick Sebel

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737

Abstract: A bipolar transistor and a method of making a bipolar transistor. The method includes providing a semiconductor substrate having a major surface, one or more layers located beneath the major surface for forming an intrinsic base, and a collector. The method also includes depositing a first oxide layer on the major surface, depositing a second oxide layer on the first oxide layer, and depositing an extrinsic base layer on the second oxide layer. The method further includes forming an emitter window through the extrinsic base layer. The method also includes removing at least a part of the second oxide layer to form a first cavity and forming an initial part of a base link region in the first cavity. The method also includes removing at least a part of the first oxide layer to form a second cavity and filling the second cavity to form a completed base link region.

公开(公告)号：US11901414B2

公开(公告)日：2024-02-13

申请号：US17447018

申请日：2021-09-07

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Viet Thanh Dinh ,  Petrus Hubertus Cornelis Magnee

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/1004 ,  H01L29/0821 ,  H01L29/7375

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.

公开(公告)号：US20230081675A1

公开(公告)日：2023-03-16

申请号：US17447018

申请日：2021-09-07

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Viet Thanh Dinh ,  Petrus Hubertus Cornelis Magnee

IPC: H01L29/10 ,  H01L29/737 ,  H01L29/08

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.

公开(公告)号：US10418483B2

公开(公告)日：2019-09-17

申请号：US15797450

申请日：2017-10-30

Applicant: NXP B.V.

Inventor： Bernhard Grote ,  Xin Lin ,  Saumitra Raj Mehrotra ,  Ljubo Radic ,  Ronghua Zhu

IPC: H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/36 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

公开(公告)号：US12107143B2

公开(公告)日：2024-10-01

申请号：US17813504

申请日：2022-07-19

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Johannes Josephus Theodorus Marinus Donkers ,  Bernhard Grote

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7375 ,  H01L29/7378

Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.

公开(公告)号：US20240178304A1

公开(公告)日：2024-05-30

申请号：US18059849

申请日：2022-11-29

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Jay Paul John ,  James Albert Kirchgessner ,  Johannes Josephus Theodorus Marinus Donkers

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/1004 ,  H01L29/66234

Abstract: A semiconductor device includes a semiconductor substrate, a collector region formed within the semiconductor substrate in a first semiconductor region having an upper surface and a collector sidewall, a base region disposed over the collector region, a seed region formed over the semiconductor substrate and coupled to the semiconductor substrate outside the base region, an extrinsic base region having an upper surface and formed over the seed region and electrically coupled to the base region, and an emitter region formed over the base region.

公开(公告)号：US20240055314A1

公开(公告)日：2024-02-15

申请号：US17818607

申请日：2022-08-09

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Richard Emil Sweeney ,  Vikas Shilimkar ,  Bernhard Grote ,  Darrell Glenn Hill ,  Ibrahim Khalil

IPC: H01L23/367 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L23/367 ,  H01L29/2003 ,  H01L29/7786

Abstract: A transistor formed in a semiconductor substrate is provided with a cooling trench. The cooling trench is elongated and extends laterally from a first end of an elongated gate electrode disposed above a channel region of the transistor to a second end of the gate electrode in a first direction that is parallel to a top surface of the semiconductor substrate. The cooling trench is coupled to the first current terminal and extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.

公开(公告)号：US20180151723A1

公开(公告)日：2018-05-31

申请号：US15797450

申请日：2017-10-30

Applicant: NXP B.V.

Inventor： Bernhard Grote ,  Xin Lin ,  Saumitra Raj Mehrotra ,  Ljubo Radic ,  Ronghua Zhu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L21/761 ,  H01L21/265

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/7835

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.