公开(公告)号：US20170149388A1

公开(公告)日：2017-05-25

申请号：US15342009

申请日：2016-11-02

Applicant: NXP B.V.

Inventor： Shagun Bajoria ,  Muhammed Bolatkale ,  Robert Rutten ,  Lucien Breems ,  Johannes Brekelmans ,  Jan Niehof

IPC: H03D7/12 ,  H03M3/00

CPC classification number: H03D7/12 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/331 ,  H03F2203/45138 ,  H03M3/422 ,  H03M3/454 ,  H03M3/476

Abstract: A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.