公开(公告)号：US20170150521A1

公开(公告)日：2017-05-25

申请号：US15356451

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Jan Niehof ,  Shagun Bajoria ,  Muhammed Bolatkale ,  Robert Rutten ,  Lucien Johannes Breems ,  Johannes Hubertus Antonius Brekelmans

IPC: H04W74/00 ,  H04L5/00

CPC classification number: H04W74/002 ,  H03M1/0678 ,  H03M1/08 ,  H03M1/123 ,  H03M1/183 ,  H04L5/0051

Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.

公开(公告)号：US20170149388A1

公开(公告)日：2017-05-25

申请号：US15342009

申请日：2016-11-02

Applicant: NXP B.V.

Inventor： Shagun Bajoria ,  Muhammed Bolatkale ,  Robert Rutten ,  Lucien Breems ,  Johannes Brekelmans ,  Jan Niehof

IPC: H03D7/12 ,  H03M3/00

CPC classification number: H03D7/12 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/331 ,  H03F2203/45138 ,  H03M3/422 ,  H03M3/454 ,  H03M3/476

Abstract: A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.

公开(公告)号：US10098146B2

公开(公告)日：2018-10-09

申请号：US15356451

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Jan Niehof ,  Shagun Bajoria ,  Muhammed Bolatkale ,  Robert Rutten ,  Lucien Johannes Breems ,  Johannes Hubertus Antonius Brekelmans

IPC: H04W74/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H04L5/00 ,  H03M1/18

Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.

公开(公告)号：US09906384B1

公开(公告)日：2018-02-27

申请号：US15275968

申请日：2016-09-26

Applicant: NXP B.V.

Inventor： Robert Rutten ,  Lucien Johannes Breems ,  Johannes Hubertus Antonius Brekelmans ,  Jan Niehof ,  Muhammed Bolatkale ,  Shagun Bajoria

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H03D3/009 ,  H04L27/3863 ,  H04L2025/0349 ,  H04L2025/03808

Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.