公开(公告)号：US12231136B2

公开(公告)日：2025-02-18

申请号：US17655399

申请日：2022-03-18

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/189 ,  H03C3/09 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

公开(公告)号：US11114978B2

公开(公告)日：2021-09-07

申请号：US17061887

申请日：2020-10-02

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso

IPC: H03B5/12 ,  H03C3/09

Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus includes a plurality of unit variable reactance structures including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.

公开(公告)号：US20150255630A1

公开(公告)日：2015-09-10

申请号：US14635018

申请日：2015-03-02

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mathieu Perin ,  Laure Rolland du Roscoat

IPC: H01L29/93 ,  H01L29/423

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/423 ,  H01L29/66174 ,  H01L29/94 ,  H01L2924/0002 ,  H03B5/124 ,  H03B5/1243 ,  H01L2924/00

Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.

Abstract translation: 一种MOS变容二极管结构，包括具有阱区和多个栅电极的半导体本体和布置在阱区上的多个阴极，其中栅电极包括细长焊盘，并且多个阴极触点通过阴极连接 阴极连接图案包括多个臂，所述多个臂中的每一个布置成在相应的栅电极焊盘的一部分上延伸。

公开(公告)号：US11545982B2

公开(公告)日：2023-01-03

申请号：US17656124

申请日：2022-03-23

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/085 ,  H03L7/099

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

公开(公告)号：US09391214B2

公开(公告)日：2016-07-12

申请号：US14635018

申请日：2015-03-02

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mathieu Perin ,  Laure Rolland du Roscoat

IPC: H01L29/93 ,  H03B5/12 ,  H01L29/66 ,  H01L27/08 ,  H01L29/94 ,  H01L29/423 ,  H01L23/482

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/423 ,  H01L29/66174 ,  H01L29/94 ,  H01L2924/0002 ,  H03B5/124 ,  H03B5/1243 ,  H01L2924/00

Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.

Abstract translation: 一种MOS变容二极管结构，包括具有阱区和多个栅电极的半导体本体和布置在阱区上的多个阴极，其中栅电极包括细长焊盘，并且多个阴极触点通过阴极连接 阴极连接图案包括多个臂，所述多个臂中的每一个布置成在相应的栅电极焊盘的一部分上延伸。

公开(公告)号：US20220321132A1

公开(公告)日：2022-10-06

申请号：US17656124

申请日：2022-03-23

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/085 ,  H03L7/099

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

公开(公告)号：US20220311446A1

公开(公告)日：2022-09-29

申请号：US17655399

申请日：2022-03-18

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/10

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

公开(公告)号：US20210126584A1

公开(公告)日：2021-04-29

申请号：US17061887

申请日：2020-10-02

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso

IPC: H03B5/12

Abstract: A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.