公开(公告)号：US10998490B2

公开(公告)日：2021-05-04

申请号：US16606927

申请日：2018-04-05

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Rie Matsumoto ,  Takayuki Nozaki ,  Shinji Yuasa ,  Hiroshi Imamura

IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10

Abstract: A magnetic element includes a first magnetic layer and a first nonmagnetic layer. An angle θ0 between a first direction and the magnetization direction of the first magnetic layer satisfies 0°

公开(公告)号：US20150280111A1

公开(公告)日：2015-10-01

申请号：US14423978

申请日：2013-08-27

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shinji Yuasa ,  Takayuki Nozaki

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetic multilayer film, includes a nonmagnetic layer including a single- or poly-crystalline magnesium oxide in which a (001) crystal plane is preferentially oriented, a very thin layer including an oxide of a 3d transition metal element, and a very thin ferromagnetic layer, laminated in sequence starting on a substrate side.

Abstract translation: 磁性多层膜包括非磁性层，其包括其中（001）晶面优先取向的单晶或多晶氧化镁，包括3d过渡金属元素的氧化物的非常薄的层，以及非常薄的铁磁性 层，从衬底侧开始层叠。

公开(公告)号：US11031062B2

公开(公告)日：2021-06-08

申请号：US16603343

申请日：2018-04-04

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Yoichi Shiota ,  Takayuki Nozaki ,  Shinji Yuasa

IPC: G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10

Abstract: According to one embodiment, a magnetic memory device includes a stacked body and a controller. The stacked body includes a first conductive layer, a second conductive layer, a first magnetic layer provided between the first conductive layer and the second conductive layer, a second magnetic layer provided between the first magnetic layer and the second conductive layer, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A resistance value per unit area of the nonmagnetic layer exceeds 20 Ωμm2. The controller is electrically connected to the first conductive layer and the second conductive layer, and supplies a write pulse to the stacked body in a first operation. The write pulse includes a rise period, a potential of the write pulse changing from a first potential toward a second potential in the rise period, an intermediate period of the second potential after the rise period, and a fall period after the intermediate period, the potential of the write pulse changing from the second potential toward the first potential in the fall period. A duration of the fall period is longer than a duration of the rise period.

公开(公告)号：US11133459B2

公开(公告)日：2021-09-28

申请号：US16498936

申请日：2018-02-15

Applicant: National Institute of Advanced Industrial Science and Technology ,  TOHOKU UNIVERSITY ,  NATIONAL INSTITUTE FOR MATERIALS SCIENCE

Inventor： Takayuki Nozaki ,  Shinji Yuasa ,  Rachwal Anna Koziol ,  Masahito Tsujikawa ,  Masafumi Shirai ,  Kazuhiro Hono ,  Tadakatsu Ohkubo ,  Xiandong Xu

IPC: H01L43/10 ,  H01F10/14 ,  H01F10/30 ,  H01L27/22 ,  H01L29/82

Abstract: According to one embodiment, a magnetic element includes a first layer and a second layer. The first layer includes a first element and a second element. The first element includes at least one selected from the group consisting of Fe, Co, and Ni. The second element includes at least one selected from the group consisting of Ir and Os. The second layer is nonmagnetic.

公开(公告)号：US10431303B2

公开(公告)日：2019-10-01

申请号：US15827626

申请日：2017-11-30

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Takayuki Nozaki ,  Yoshishige Suzuki ,  Shinji Yuasa ,  Yoichi Shiota ,  Takurou Ikeura ,  Hiroki Noguchi ,  Kazutaka Ikegami

IPC: G11C13/00 ,  G11C11/16

Abstract: A resistance change type memory includes a variable resistance element connected between first and second bit lines and a write control circuit including first and second transistors each including a terminal connected to the first bit line. The write control circuit controls write to the variable resistance element. The write control circuit supplies a second voltage to the first bit line with a first pulse width via the second transistor in the ON state after supplying a first voltage to the first bit line via the first transistor.