公开(公告)号：US07212525B2

公开(公告)日：2007-05-01

申请号：US10046304

申请日：2002-01-16

申请人： Norihiko Moriwaki ,  Hidehiro Toyoda

发明人： Norihiko Moriwaki ,  Hidehiro Toyoda

IPC分类号： H04L12/50 ,  H04Q11/00

CPC分类号： H04L49/352 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/254 ,  H04L49/3045 ,  H04L49/552

摘要： A Packet communication system has a first line interface; a second line interface that accommodates lines slower than lines accommodated by the first line interface; a crossbar switch; and a scheduler that periodically receives packet output requests from the first and second line interfaces and sends grants based on the requests for the crossbar switch to the first and second line interfaces. The link capacity between the first line interface and the crossbar switch is made higher than that between the second line interface and the crossbar switch, whereby a packet communication system capable of accommodating line interfaces with different speeds efficiently can be provided.

摘要翻译： 分组通信系统具有第一线路接口; 第二线路接口，其容纳比由第一线路接口容纳的线路慢的线路; 横梁开关; 以及调度器，其周期性地从所述第一和第二线路接口接收分组输出请求，并且基于对所述第一和第二线路接口的交叉开关的请求来发送授权。 第一线路接口和交叉开关之间的链路容量比第二线路接口和交叉开关之间的链路容量高，从而可以提供能够有效地适应不同速度的线路接口的分组通信系统。

公开(公告)号：US07120160B2

公开(公告)日：2006-10-10

申请号：US10042351

申请日：2002-01-11

申请人： Masayuki Takase ,  Hidehiro Toyoda ,  Norihiko Moriwaki

发明人： Masayuki Takase ,  Hidehiro Toyoda ,  Norihiko Moriwaki

IPC分类号： H04L12/56

CPC分类号： H04L49/3045 ,  H04L49/101 ,  H04L49/254 ,  H04L49/50

摘要： A packet switching system arbitrates between Virtual Output Queues (VoQ) in plural input buffers, so as to grant the right of transmitting data to a crossbar switch to some of the VoQs by taking both an output data interval of a VoQ and the queue length of a VoQ as parameters. The system suppresses the delay time of the segment of a VoQ having a high load, thereby preventing buffers from overflowing; and, also, the system permits a VoQ having a low load to transmit segments under no influence of the VoQ that has a high load and is just reading out the segment.

摘要翻译： 分组交换系统在多个输入缓冲器中的虚拟输出队列（VoQ）之间进行仲裁，以便通过同时获取VoQ的输出数据间隔和VoQ的队列长度来授予向某些VoQ发送数据到交叉开关的权利 一个VoQ作为参数。 该系统抑制具有高负载的VoQ的段的延迟时间，从而防止缓冲器溢出; 并且，该系统还允许具有低负载的VoQ在没有高负载的VoQ的影响下传输段，并且刚刚读出该段。

公开(公告)号：US06999413B2

公开(公告)日：2006-02-14

申请号：US09940476

申请日：2001-08-29

申请人： Norihiko Moriwaki ,  Hidehiro Toyoda ,  Masayuki Takase

发明人： Norihiko Moriwaki ,  Hidehiro Toyoda ,  Masayuki Takase

IPC分类号： G01R31/08

CPC分类号： H04L49/101 ,  H04L49/1523 ,  H04L49/1576 ,  H04L49/3027 ,  H04L49/3045 ,  H04L49/3072 ,  H04L49/45

摘要： A packet switch has a switch section formed by a plurality of crossbar switch planes and plurality of interfaces, and each interface outputs in parallel input packets in block units to the plurality of crossbar switch planes in response to signals from a scheduler, wherein when n crossbar switch planes can be mounted on the packet switch, each interface allocates time slots corresponding to the n crossbar switch planes or when a switch plane is additionally mounted, a block is read at a time slot corresponding to the additional switch plane or when a switch plane is stopped from working, an idle time slot is used to prevent a block from being output to the switch plane which is unused.

公开(公告)号：US07685496B2

公开(公告)日：2010-03-23

申请号：US10579047

申请日：2004-07-22

申请人： Hidehiro Toyoda

发明人： Hidehiro Toyoda

IPC分类号： H03M13/00

CPC分类号： H04L1/0057 ,  H04J14/02 ,  H04J14/0226 ,  H04J14/0279 ,  H04L1/0041 ,  H04L2001/0096

摘要： In a method for data transmission, which transmits data through a transmission line, which integrates a plurality of links into one transmission line, a first link group, which transmits information data by at least one link out of a plurality of links, a second link group, which transmits parity data generated by the information data by at least one link out of a plurality of links, which are different from the first link group, and a third link group, which generates an error check data related to an error correction from the information data or the parity data, when an error occurs in the information data or the parity data, and transmits by at least one link out of a plurality of links, which are different from the first link group and the second link group, are integrated and transmitted.

摘要翻译： 在通过将多个链路集成到一个传输线中的传输线传输数据的数据传输方法中，通过多个链路中的至少一个链路发送信息数据的第一链路组，第二链路 组，其通过由与第一链路组不同的多个链路中的至少一个链路发送由信息数据生成的奇偶校验数据;以及第三链路组，其生成与错误校正有关的错误校验数据， 信息数据或奇偶校验数据，当在信息数据或奇偶校验数据中出现错误时，通过与第一链路组和第二链路组不同的多个链路中的至少一个链路进行发送时， 集成和传输。

公开(公告)号：US20080056342A1

公开(公告)日：2008-03-06

申请号：US11782705

申请日：2007-07-25

申请人： KOJI FUJUDA ,  Hidehiro Toyoda ,  Hiroki Yamashita

发明人： KOJI FUJUDA ,  Hidehiro Toyoda ,  Hiroki Yamashita

IPC分类号： H03H21/00

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10194 ,  G11B20/10481 ,  G11B2220/2537

摘要： In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.

摘要翻译： 在脉冲宽度控制均衡中，注意前后信号的对称性的存在，从而将存储边缘位置的调整量的表的尺寸减小到二分之一的幂。 由符号间干扰引起的模式抖动被抑制。 每个符号的脉冲时间间隔被调整为由计算公式确定的最佳脉冲宽度或响应于要发送的代码序列在表中搜索。 在使用表格的结构中，存储边缘位置调整量的表，其中位于现在准备好以代码序列发送的中心符号之前和之后彼此对称的两个符号的异或的行 被用作搜索键。

公开(公告)号：US08855148B2

公开(公告)日：2014-10-07

申请号：US13586076

申请日：2012-08-15

申请人： Hidehiro Toyoda ,  Masashi Kono

发明人： Hidehiro Toyoda ,  Masashi Kono

IPC分类号： H04J3/02 ,  H04L29/04 ,  H04L12/26 ,  H04B1/00 ,  H03K17/00 ,  H04J3/00

CPC分类号： H04L12/26 ,  H03K17/00 ,  H03L7/081 ,  H03L7/1976 ,  H04B1/00 ,  H04J3/00 ,  H04J3/047 ,  H04J3/062 ,  H04J3/0685 ,  H04L29/04 ,  H04L43/00

摘要： Digital signals having respective pieces of frequency information different from each other are bundled, and transmitted at high speed. On receiving side, digital signals retaining the respective pieces of frequency information are recovered and separated. Transmitter apparatus divides pieces of transmission data that have the different pieces of frequency information and correspond to respective input channels into data blocks having a fixed length, as valid data, and subsequently multiplexes the data blocks corresponding to the respective input channels and outputs the multiplexed data to a transmission path. A receiver apparatus divides data string received into data flows and subsequently restores the transmission data, from the data blocks consecutive in each data flow and stores the restored data, and outputs transmission data corresponding to the respective data flows in synchronization with clocks generated for these data flows.

摘要翻译： 具有彼此不同的各个频率信息的数字信号被捆扎，并以高速发送。 在接收侧，保存各个频率信息的数字信号被恢复和分离。 发射机设备将具有不同频率信息的传输数据片段与对应于输入信道的传输数据分成具有固定长度的数据块作为有效数据，然后将与各个输入信道相对应的数据块多路复用，并输出多路复用数据 到传输路径。 接收机设备将接收到的数据串分成数据流，然后从每个数据流中连续的数据块中恢复发送数据，并存储恢复的数据，并且与为这些数据生成的时钟同步地输出与各个数据流对应的发送数据 流动。

公开(公告)号：US08498204B2

公开(公告)日：2013-07-30

申请号：US12716451

申请日：2010-03-03

申请人： Hidehiro Toyoda ,  Shinji Murai

发明人： Hidehiro Toyoda ,  Shinji Murai

IPC分类号： H04L12/26

CPC分类号： H04L43/065 ,  H04L1/20 ,  H04L41/0677

摘要： It is provided a data transmission system comprising a transmitter, a repeater and a receiver. The transmitter and the repeater are coupled through a first transmission path and the receiver and the repeater are coupled through a second transmission path. The transmitter, the repeater and the receiver have virtual lanes. The transmitter demultiplexes the transmission data into as many data streams as a number of useable virtual lanes based on useable lane information. The repeater monitors failures of the transmission lanes of the first transmission path and the virtual lanes. The receiver monitors failures of the transmission lanes of the second transmission path and the virtual lanes, selects the useable virtual lanes, sends to the transmitter the useable lane information, corrects a wrong order of the received data streams and a shift of reception point in the virtual lanes, and restores the demultiplexed data streams into the transmission data.

摘要翻译： 提供了一种包括发射机，中继器和接收机的数据传输系统。 发射机和中继器通过第一传输路径耦合，并且接收机和中继器通过第二传输路径耦合。 发射机，中继器和接收机都有虚拟通道。 发射机基于可用的车道信息将传输数据解复用成与许多可用的虚拟车道一样多的数据流。 中继器监视第一传输路径和虚拟通道的传输通道的故障。 接收机监视第二传输路径和虚拟通道的传输通道的故障，选择可用的虚拟通道，向发射机发送可用的车道信息，校正接收到的数据流的错误顺序和接收点的移位 虚拟通道，并将解复用的数据流恢复为传输数据。

公开(公告)号：US08281207B2

公开(公告)日：2012-10-02

申请号：US12515176

申请日：2006-11-17

申请人： Hidehiro Toyoda ,  Takayuki Muranaka ,  Takeshi Matsumoto ,  Naohisa Koie

发明人： Hidehiro Toyoda ,  Takayuki Muranaka ,  Takeshi Matsumoto ,  Naohisa Koie

IPC分类号： H03M13/00

CPC分类号： H03M13/19

摘要： A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.

摘要翻译： 发射机与接收机通信，误差校正器校正数据传输期间产生的比特错误。 发射机具有扰频单元，用于加扰数据，使得输入数据中的0和1的运行视差基本上为零。 一个比特串转换单元15，其添加用于确保加扰数据的串行比特串的最大游程长度的比特数据，并将控制信息转换成固定值的比特数据。 同步定时生成单元16将发送的数据以恒定的间隔分割，并将发送数据转换为数据块。 位串转换单元从数据块的位串中提取控制数据的固定值位模式，将位模式转换为控制信息，并对数据和控制信息进行鉴别。 解扰器单元将数据加扰的数据重新转换为加扰之前的数据。

公开(公告)号：US20060269025A1

公开(公告)日：2006-11-30

申请号：US11350085

申请日：2006-02-09

申请人： Hidehiro Toyoda

发明人： Hidehiro Toyoda

IPC分类号： H04B1/10 ,  G06F17/10

CPC分类号： H03H17/06 ,  H03H17/0294 ,  H03H2220/08 ,  H04B3/10

摘要： Provided is a transversal filter, in which delayers and multipliers are connected in series, includes: a first multiplier for multiplying a first tap coefficient set by a tap coefficient register module and an input signal to output a result of multiplication; a first delayer for delaying the value output from the first multiplier by a predetermined time to output the delayed value; a second multiplier for multiplying a second tap coefficient set by the tap coefficient register module and an input signal to output a result of multiplication; a first adder for adding the value output from the delayer situated upstream to the value output from the second multiplier to output a result of addition; a second delayer for delaying the value output from the first adder by a predetermined time to output the delayed value; and a selector for selecting one of the input signal, the value output from the first delayer, and the value output from the second delayer to output the selected one.

摘要翻译： 提供了一种横向滤波器，其中延迟器和乘法器串联连接，包括：用于将由抽头系数寄存器模块设置的第一抽头系数与输入信号相乘以输出乘法结果的第一乘法器; 第一延迟器，用于将从第一乘法器输出的值延迟预定时间以输出延迟值; 用于将由抽头系数寄存器模块设置的第二抽头系数与输入信号相乘以输出乘法结果的第二乘法器; 第一加法器，用于将从位于上游的延迟器输出的值相加于从第二乘法器输出的值，以输出相加结果; 第二延迟器，用于将从第一加法器输出的值延迟预定时间以输出延迟值; 以及选择器，用于选择输入信号之一，从第一延迟器输出的值和从第二延迟器输出的值以输出所选择的输入信号。

公开(公告)号：US08005130B2

公开(公告)日：2011-08-23

申请号：US11826300

申请日：2007-07-13

申请人： Hidehiro Toyoda ,  Tatsuya Saito ,  Hiroki Yamashita ,  Norio Chujo

发明人： Hidehiro Toyoda ,  Tatsuya Saito ,  Hiroki Yamashita ,  Norio Chujo

IPC分类号： H04B1/38

CPC分类号： H04L7/0337

摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.

摘要翻译： 一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。 在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从 时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。