公开(公告)号：US08279669B2

公开(公告)日：2012-10-02

申请号：US12855243

申请日：2010-08-12

申请人： Norihiro Fujita ,  Yasuyuki Fukuda

发明人： Norihiro Fujita ,  Yasuyuki Fukuda

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3427 ,  G11C2211/5621

摘要： According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first cell and the second cell. The second buffer holds read data from the first cell. The controller controls first writing and rewriting executed for the first cell and second writing executed for the second cell. The write data in the first buffer is updated each time a second write signal is given. The controller executes the first writing based on the write data held by the first buffer. The controller performs the second writing based on the write data updated in the first buffer. The controller executes the rewriting based on the read data held by the second buffer.

摘要翻译： 根据一个实施例，半导体存储装置包括第一单元，第二单元，位线，第一缓冲器，第二缓冲器和控制器。 位线将数据传送到第一个单元和第二个单元。 第一缓冲器将写数据保存到第一单元和第二单元。 第二缓冲器保存来自第一个单元的读取数据。 控制器控制对第一单元执行的第一次写入和重写以及为第二单元执行的第二次写入。 每当给出第二写入信号时，更新第一缓冲器中的写入数据。 控制器基于由第一缓冲器保持的写入数据执行第一次写入。 控制器基于在第一缓冲器中更新的写入数据执行第二次写入。 控制器基于由第二缓冲器保持的读取数据执行重写。

公开(公告)号：US07965556B2

公开(公告)日：2011-06-21

申请号：US12788614

申请日：2010-05-27

申请人： Norihiro Fujita ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

发明人： Norihiro Fujita ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

摘要翻译： 非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据 复制，被复制到第二个内存。

公开(公告)号：US20080170435A1

公开(公告)日：2008-07-17

申请号：US12015755

申请日：2008-01-17

申请人： Naoya Tokiwa ,  Norihiro Fujita

发明人： Naoya Tokiwa ,  Norihiro Fujita

IPC分类号： G11C16/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.

摘要翻译： 存储单元阵列具有布置在其中的多个多值存储器单元，其可以将一个存储单元中的两位或更多位的信息存储为不同的页。 在每个数据寄存器中，临时保存从存储单元阵列读取的数据的可接受数量设置寄存器存储与多值存储器单元中的每个页的阈值电压的每种状态相对应的多个可接受数量的数据状态 。 选择器从多个可接受数量的数据状态中选择对应于多值存储器单元的每一页的每个数据寄存器中保留的数据的可接受数量的数据状态。 比较器将每个数据寄存器中保留的数据状态数与选择器选择的可接受的数据状态数进行比较。

公开(公告)号：US08274836B2

公开(公告)日：2012-09-25

申请号：US13010165

申请日：2011-01-20

申请人： Yoshikazu Harada ,  Norihiro Fujita ,  Masaki Fujiu

发明人： Yoshikazu Harada ,  Norihiro Fujita ,  Masaki Fujiu

IPC分类号： G11C16/06

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.

摘要翻译： 提供一种具有抑制多层存储器系统的非易失性半导体存储器件的错误读取的单元的非易失性半导体存储器件和非易失性存储器系统。 在多级存储器系统的非易失性半导体存储器件和非易失性存储器系统中，当在封装处理之前写入数据时，使用第一验证电压，并将验证电压切换到低于第一校验电压的第二验证电压 在包装过程中写入数据时的电压。

公开(公告)号：US20100165744A1

公开(公告)日：2010-07-01

申请号：US12723057

申请日：2010-03-12

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US20060034140A1

公开(公告)日：2006-02-16

申请号：US11194608

申请日：2005-08-02

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C8/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

公开(公告)号：US08315104B2

公开(公告)日：2012-11-20

申请号：US12491638

申请日：2009-06-25

申请人： Takuya Futatsuyama ,  Toshiaki Edahiro ,  Norihiro Fujita ,  Fumitaka Arai ,  Tohru Maruyama ,  Masaki Kondo

发明人： Takuya Futatsuyama ,  Toshiaki Edahiro ,  Norihiro Fujita ,  Fumitaka Arai ,  Tohru Maruyama ,  Masaki Kondo

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

摘要翻译： 非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作 在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压 验证操作。

公开(公告)号：US08300474B2

公开(公告)日：2012-10-30

申请号：US13298610

申请日：2011-11-17

申请人： Norihiro Fujita

发明人： Norihiro Fujita

IPC分类号： G11C11/34

CPC分类号： G11C29/025 ,  G06F11/073 ,  G06F11/0751 ,  G11C16/04 ,  G11C16/3422 ,  G11C29/50004 ,  G11C2029/1202

摘要： According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memory cell after storing of program data is judged to be completed by a verify circuit, and output a status information indicating that a program operation has passed to a external controller when data read by a read operation and a program data match and the status information indicating that the program operation has failed to the external controller when both do not match. A data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括控制电路。 控制电路被配置为重复对所选字线的写入脉冲和验证读取操作的应用，在存储程序数据被判定为由验证电路完成之后，从选择的存储器单元执行读取操作，并且输出 指示当通过读取操作和程序数据读取的数据匹配时的程序操作已经传递到外部控制器的状态信息以及当两者都不匹配时指示程序操作对外部控制器失败的状态信息。 即使在通过验证电路判断存储程序数据后，数据锁存电路继续锁存程序数据。

公开(公告)号：US20120045055A1

公开(公告)日：2012-02-23

申请号：US13206778

申请日：2011-08-10

申请人： Norihiro Fujita

发明人： Norihiro Fujita

IPC分类号： H04L9/16

CPC分类号： H04L63/0428 ,  H04L63/0869

摘要： There is provided a communication device including a change request reception unit for receiving a change request for temporarily changing an encryption type of the communication device transmitted from an information processing device, an encryption type change unit for temporarily changing the encryption type of the communication device on the basis of the change request received by the change request reception unit, and an authentication information transmission unit for transmitting authentication information for causing the information processing device to authenticate the communication device encrypted in the encryption type temporarily changed by the encryption type change unit to the information processing device.

摘要翻译： 提供了一种通信装置，包括：改变请求接收单元，用于接收用于暂时改变从信息处理设备发送的通信设备的加密类型的改变请求，用于临时改变通信设备的加密类型的加密类型改变单元 所述更改请求接收单元接收到的改变请求的基础，以及认证信息发送单元，用于发送用于使所述信息处理设备认证由所述加密类型改变单元暂时改变的加密类型加密的所述通信设备认证到 信息处理装置。

公开(公告)号：US20090323432A1

公开(公告)日：2009-12-31

申请号：US12491638

申请日：2009-06-25

申请人： Takuya Futatsuyama ,  Toshiaki Edahiro ,  Norihiro Fujita ,  Fumitaka Arai ,  Tohru Maruyama ,  Masaki Kondo

发明人： Takuya Futatsuyama ,  Toshiaki Edahiro ,  Norihiro Fujita ,  Fumitaka Arai ,  Tohru Maruyama ,  Masaki Kondo

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/3454 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

摘要翻译： 非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作 在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压 验证操作。