公开(公告)号：US07577030B2

公开(公告)日：2009-08-18

申请号：US12015755

申请日：2008-01-17

申请人： Naoya Tokiwa ,  Norihiro Fujita

发明人： Naoya Tokiwa ,  Norihiro Fujita

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.

摘要翻译： 存储单元阵列具有布置在其中的多个多值存储器单元，其可以将一个存储单元中的两位或更多位的信息存储为不同的页。 在每个数据寄存器中，临时保存从存储单元阵列读取的数据的可接受数量设置寄存器存储与多值存储器单元中的每个页的阈值电压的每种状态相对应的多个可接受数量的数据状态 。 选择器从多个可接受数量的数据状态中选择对应于多值存储器单元的每一页的每个数据寄存器中保留的数据的可接受数量的数据状态。 比较器将每个数据寄存器中保留的数据状态数与选择器选择的可接受的数据状态数进行比较。

公开(公告)号：US20080170435A1

公开(公告)日：2008-07-17

申请号：US12015755

申请日：2008-01-17

申请人： Naoya Tokiwa ,  Norihiro Fujita

发明人： Naoya Tokiwa ,  Norihiro Fujita

IPC分类号： G11C16/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.

摘要翻译： 存储单元阵列具有布置在其中的多个多值存储器单元，其可以将一个存储单元中的两位或更多位的信息存储为不同的页。 在每个数据寄存器中，临时保存从存储单元阵列读取的数据的可接受数量设置寄存器存储与多值存储器单元中的每个页的阈值电压的每种状态相对应的多个可接受数量的数据状态 。 选择器从多个可接受数量的数据状态中选择对应于多值存储器单元的每一页的每个数据寄存器中保留的数据的可接受数量的数据状态。 比较器将每个数据寄存器中保留的数据状态数与选择器选择的可接受的数据状态数进行比较。

公开(公告)号：US09003242B2

公开(公告)日：2015-04-07

申请号：US13428089

申请日：2012-03-23

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G06F11/00 ,  G11C29/44 ,  G11C13/00

CPC分类号： G11C29/44 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2029/4402

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，第一寄存器，被配置为存储存储单元的数据;以及序列控制电路，被配置为控制存储单元阵列和第一寄存器。 在存储器单元的至少一个数据读取操作中，顺序控制电路从存储单元阵列读出包括表示故障位数是否在允许范围内的标志信息的数据。

公开(公告)号：US08228733B2

公开(公告)日：2012-07-24

申请号：US13164938

申请日：2011-06-21

申请人： Naoya Tokiwa ,  Hideo Mukai

发明人： Naoya Tokiwa ,  Hideo Mukai

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/1202 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

摘要翻译： 本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱 其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元， 具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于 对应于地址信号的字线。

公开(公告)号：US20120026804A1

公开(公告)日：2012-02-02

申请号：US13271645

申请日：2011-10-12

申请人： Hiroyuki NAGASHIMA ,  Naoya Tokiwa

发明人： Hiroyuki NAGASHIMA ,  Naoya Tokiwa

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C5/04 ,  G11C8/04 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

摘要翻译： 半导体存储器件包括多层布置的多个存储层，每个存储层包括一个单元阵列，该单元阵列包含多条第一平行线，多条第二平行线与第一条线交叉，以及多个存储器 在第一线和第二线的交叉处连接的细胞; 脉冲发生器，用于产生数据访问存储单元所需的脉冲; 以及控制装置，用于控制脉冲发生器，使得从脉冲发生器输出的脉冲具有与存取目标存储单元所属的存储层相对应的能量。

公开(公告)号：US07986557B2

公开(公告)日：2011-07-26

申请号：US12533529

申请日：2009-07-31

申请人： Naoya Tokiwa ,  Shigeo Ohshima

发明人： Naoya Tokiwa ,  Shigeo Ohshima

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/143 ,  G11C5/145 ,  G11C8/06 ,  G11C8/10 ,  G11C16/0483

摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

摘要翻译： 存储器可以包括字线; 位线 对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

公开(公告)号：US20110134681A1

公开(公告)日：2011-06-09

申请号：US13027798

申请日：2011-02-15

申请人： Hiroyuki NAGASHIMA ,  Naoya Tokiwa

发明人： Hiroyuki NAGASHIMA ,  Naoya Tokiwa

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C5/04 ,  G11C8/04 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multi layer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

摘要翻译： 半导体存储器件包括多层布置的多个存储层，每个存储层包括一个单元阵列，该单元阵列包含多条第一平行线，多条第二平行线与第一条线交叉， 存储单元连接在第一行和第二行的交点处; 脉冲发生器，用于产生数据访问存储单元所需的脉冲; 以及控制装置，用于控制脉冲发生器，使得从脉冲发生器输出的脉冲具有与存取目标存储单元所属的存储层相对应的能量。

公开(公告)号：US07864586B2

公开(公告)日：2011-01-04

申请号：US12277698

申请日：2008-11-25

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C16/20

摘要： A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area.

摘要翻译： 非易失性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 配置为存储用于控制存储器操作的控制数据的第一寄存器组; 在所述存储单元阵列中定义的调整数据存储区域，以存储用于调整所述控制数据的调整数据; 以及第二寄存器组，被配置为存储从调整数据存储区域读取的调整数据。

公开(公告)号：US20080212370A1

公开(公告)日：2008-09-04

申请号：US12040155

申请日：2008-02-29

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.

摘要翻译： 公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路 ，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于 命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

公开(公告)号：US20050201156A1

公开(公告)日：2005-09-15

申请号：US10874361

申请日：2004-06-24

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/02 ,  G11C16/06

CPC分类号： G11C16/22

摘要： A nonvolatile semiconductor memory device with a function of executing a verify operation for write data that is input from outside includes a memory cell array including memory cells arranged in a matrix, and a password storage area for storing password data, an input buffer that receives data input from outside, a first retaining circuit that retains input password data or write data, which is input to the input buffer, a verify sense amplifier that detects, at a time of the verify operation, the password data that is read out of the password storage area or data that is read out of the memory cell array, and a coincidence determination circuit that determines whether the input password data coincides with the read-out password data, or determines whether the write data coincides with the read-out data.

摘要翻译： 具有执行从外部输入的写入数据的验证操作的功能的非易失性半导体存储器件包括：存储单元阵列，包括以矩阵形式排列的存储单元;以及用于存储密码数据的密码存储区域;接收数据的输入缓冲器 来自外部的输入，保持输入到输入缓冲器的输入密码数据或写入数据的第一保持电路，在验证操作时检测从密码读出的密码数据的验证读出放大器 存储区域或从存储单元阵列读出的数据，以及一致确定电路，其确定输入的密码数据是否与读出的密码数据一致，或者确定写入数据是否与读出的数据一致。