公开(公告)号：US07551450B2

公开(公告)日：2009-06-23

申请号：US10506719

申请日：2004-01-07

申请人： Norio Sugawara ,  Takashi Ando ,  Hiroaki Yamanaka

发明人： Norio Sugawara ,  Takashi Ando ,  Hiroaki Yamanaka

IPC分类号： H05K5/00

CPC分类号： H01R13/64 ,  G06K19/07732 ,  H01R13/6658 ,  H05K5/0278

摘要： An external storage apparatus capable of preventing erroneous assembly of components for which the assembly position is decided and of suppressing the occurrence of variations in its quality is provided.An external storage apparatus including a main body 11, a memory substrate 12 having a connector 24, a substrate holder 13 for fixing the memory substrate 12 to the main body under the state that the connector 24 projects outward, a cap 14 to be attachable and detachable to and from the substrate holder 13 for protecting the connector 24, wherein erroneous assembly restricting means 38, 37, 40 and 32 are provided between the main body 11, the memory substrate 12 and the substrate holder 13.

摘要翻译： 提供一种外部存储装置，其能够防止组装位置被决定的部件的错误组装和抑制其质量变化的发生。 一种外部存储装置，包括主体11，具有连接器24的存储器基板12，用于在连接器24向外突出的状态下将存储器基板12固定到主体的基板保持件13，可附接的盖14 可拆卸地连接到基板支架13和用于保护连接器24，其中错误组装限制装置38,37,40和32设置在主体11，存储器基板12和基板支架13之间。

公开(公告)号：US20050157462A1

公开(公告)日：2005-07-21

申请号：US10506719

申请日：2004-01-07

申请人： Norio Sugawara ,  Takashi Ando ,  Hiroaki Yamanaka

发明人： Norio Sugawara ,  Takashi Ando ,  Hiroaki Yamanaka

IPC分类号： G06K19/077 ,  H01R13/64 ,  H01R13/66 ,  G06F1/16 ,  H05K5/00 ,  H05K7/00

CPC分类号： H01R13/64 ,  G06K19/07732 ,  H01R13/6658 ,  H05K5/0278

摘要： An external storage apparatus capable of preventing erroneous assembly of components for which the assembly position is decided and of suppressing the occurrence of variations in its quality is provided. An external storage apparatus including a main body 11, a memory substrate 12 having a connector 24, a substrate holder 13 for fixing the memory substrate 12 to the main body under the state that the connector 24 projects outward, a cap 14 to be attachable and detachable to and from the substrate holder 13 for protecting the connector 24, wherein erroneous assembly restricting means 38, 37, 40 and 32 are provided between the main body 11, the memory substrate 12 and the substrate holder 13.

摘要翻译： 提供一种外部存储装置，其能够防止组装位置被决定的部件的错误组装和抑制其质量变化的发生。 一种外部存储装置，包括主体11，具有连接器24的存储器基板12，用于在连接器24向外突出的状态下将存储器基板12固定到主体的基板保持件13，可附接的盖14 可拆卸地连接到基板支架13和用于保护连接器24，其中错误组装限制装置38,37,40和32设置在主体11，存储器基板12和基板支架13之间。

公开(公告)号：US20050257071A1

公开(公告)日：2005-11-17

申请号：US10525904

申请日：2004-06-28

申请人： Norio Sugawara ,  Takashi Ando ,  Shigeru Kasuya

发明人： Norio Sugawara ,  Takashi Ando ,  Shigeru Kasuya

IPC分类号： G06K19/077 ,  G06F1/00 ,  G06F21/00 ,  G06K19/00 ,  G06K19/10 ,  G06T1/00 ,  H04L9/32 ,  H05K5/03

CPC分类号： G06F21/78 ,  G06F21/32

摘要： Providing a reliable, durable external storage apparatus that is capable of disposing a sensor for fingerprint authentication on its surface of the housing with a simple structure. With respect to a memory substrate 12 to be mounted a semiconductor memory 21, an image sensor 20 on which a sensing surface 20a is provided for fingerprint authentication is mounted at a surface on the opposite side to a surface where a connector 24 is mounted so as to dispose the image sensor 20 directly under a window 31. By adapting a structure such that a protective plate 13C of the substrate holder 13 is held by a holding section 58 in a vertical direction, the memory substrate 12 is protected from damages by external force acting on the substrate holder 13.

摘要翻译： 提供可靠，耐用的外部存储装置，其能够以简单的结构在壳体的表面上设置用于指纹认证的传感器。 对于要安装半导体存储器21的存储器基板12，在其上安装有用于指纹认证的感测表面20A的图像传感器20安装在与安装连接器24的表面相反的一侧的表面上 以便将图像传感器20直接放置在窗口31下方。 通过使基板保持件13的保护板13C由垂直方向上的保持部58保持的结构，可以防止存储基板12受到作用在基板保持件13上的外力的损害。

公开(公告)号：US07353992B2

公开(公告)日：2008-04-08

申请号：US10525904

申请日：2004-06-28

申请人： Norio Sugawara ,  Takashi Ando ,  Shigeru Kasuya

发明人： Norio Sugawara ,  Takashi Ando ,  Shigeru Kasuya

IPC分类号： G06K17/00

CPC分类号： G06F21/78 ,  G06F21/32

摘要： Providing a reliable, durable external storage apparatus that is capable of disposing a sensor for fingerprint authentication on its surface of the housing with a simple structure.With respect to a memory substrate 12 to be mounted a semiconductor memory 21, an image sensor 20 on which a sensing surface 20a is provided for fingerprint authentication is mounted at a surface on the opposite side to a surface where a connector 24 is mounted so as to dispose the image sensor 20 directly under a window 31. By adapting a structure such that a protective plate 13C of the substrate holder 13 is held by a holding section 58 in a vertical direction, the memory substrate 12 is protected from damages by external force acting on the substrate holder 13.

摘要翻译： 提供可靠，耐用的外部存储装置，其能够以简单的结构在壳体的表面上设置用于指纹认证的传感器。 对于要安装半导体存储器21的存储器基板12，在其上安装有用于指纹认证的感测表面20A的图像传感器20安装在与安装连接器24的表面相反的一侧的表面上 以便将图像传感器20直接放置在窗口31下方。 通过使基板保持件13的保护板13C由垂直方向上的保持部58保持的结构，可以防止存储基板12受到作用在基板保持件13上的外力的损害。

公开(公告)号：US08853413B2

公开(公告)日：2014-10-07

申请号：US13266671

申请日：2010-05-12

申请人： Yoshimasa Fukuda ,  Takashi Ando ,  Kimihiko Goto ,  Nozomu Nakanishi ,  Takashi Watanabe ,  Kenichi Kurihara ,  Nobuto Minowa ,  Masaaki Mitomi

发明人： Yoshimasa Fukuda ,  Takashi Ando ,  Kimihiko Goto ,  Nozomu Nakanishi ,  Takashi Watanabe ,  Kenichi Kurihara ,  Nobuto Minowa ,  Masaaki Mitomi

IPC分类号： C07D401/04

CPC分类号： C07D493/04

摘要： Disclosed is a process for efficiently producing pyripyropene derivatives having acyloxy at the 1-position and 11-position and hydroxyl at the 7-position. The process comprises selectively acylating hydroxyl at the 1-position and 11-position of a compound represented by formula B1 through one to three steps with an acylating agent in the presence or absence of a base.

公开(公告)号：US08786030B2

公开(公告)日：2014-07-22

申请号：US13570388

申请日：2012-08-09

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L21/02

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US08740506B2

公开(公告)日：2014-06-03

申请号：US13033253

申请日：2011-02-23

申请人： Shogo Ogaki ,  Takashi Ando ,  Masaru Inoue ,  Takeshi Shimoda

发明人： Shogo Ogaki ,  Takashi Ando ,  Masaru Inoue ,  Takeshi Shimoda

IPC分类号： B65G51/20

CPC分类号： B65G51/03 ,  B65G47/525 ,  H01L41/25

摘要： A positioning apparatus includes a stage on which a piezoelectric element is set, a stop unit having a stop face to which the piezoelectric element set on the stage is pushed so that the piezoelectric element is positioned at a target position corresponding to an attaching part of, for example, a head suspension to which the piezoelectric element is attached, and a pushing unit to push the piezoelectric element toward the stop face, the pushing unit blowing a gas to push the piezoelectric element. The positioning apparatus is capable of correctly positioning the piezoelectric element to the target position without damaging the piezoelectric element.

摘要翻译： 一种定位装置，包括设置有压电元件的台，具有止动面的停止单元，所述停止面被压入到设置在所述台上的所述压电元件，使得所述压电元件位于对应于所述平台的安装部的目标位置， 例如，安装有压电元件的磁头悬架以及将压电元件朝向止动面推压的推压单元，推压单元吹出气体来推压压电元件。 定位装置能够将压电元件正确地定位到目标位置而不损坏压电元件。

公开(公告)号：US08647972B1

公开(公告)日：2014-02-11

申请号：US13618255

申请日：2012-09-14

申请人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

发明人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

摘要： Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

摘要翻译： 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个或多个衬底和绝缘体，其包括限定沟槽的基底和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其他金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US20140008986A1

公开(公告)日：2014-01-09

申请号：US14006905

申请日：2012-03-16

申请人： Taku Miyauchi ,  Takashi Ando

发明人： Taku Miyauchi ,  Takashi Ando

IPC分类号： H02J1/10

CPC分类号： H02J1/102 ,  H02J3/383 ,  H02M3/1584 ,  H02M2001/007 ,  Y02E10/563 ,  Y10T307/707

摘要： In the present invention, first boosting circuits (41a to 41d) are interposed upon each of direct current power lines (La to Ld). The boosting ratios of the first boosting circuits (41a to 41d), for each iteration of a first cycle, are variably controlled during a first period so that the generated power of the corresponding solar cell strings (1a to 1d) is maximized, and the boosting ratios during a second period are controlled so as to be maintained at a uniform value. The total amount of time of the first period and the second period is made to correspond to the first cycle.

摘要翻译： 在本发明中，第一升压电路（41a〜41d）被插入到每条直流电力线（La〜Ld）上。 对于第一周期的每次迭代，第一升压电路（41a至41d）的升压比在第一时段期间被可变地控制，使得对应的太阳能电池串（1a至1d）的发电功率最大化，并且 控制第二期间的升压比，以保持均匀的值。 第一周期和第二周期的总时间量对应于第一周期。

公开(公告)号：US20140008983A1

公开(公告)日：2014-01-09

申请号：US14006494

申请日：2012-03-16

申请人： Taku Miyauchi ,  Takashi Ando

发明人： Taku Miyauchi ,  Takashi Ando

IPC分类号： H02J3/18

CPC分类号： H02J3/18 ,  H01L31/02021 ,  H02J1/102 ,  H02J3/385 ,  H02M2001/007 ,  Y02E10/58 ,  Y10T307/549

摘要： A current collection box includes: a number of terminals enabling the connecting of at least two solar cell strings including a plurality of solar cells are connected in series; a booster for boosting individual voltages of the generated power of each of the solar cell strings inputted via the terminals; and an output circuit for collecting all of the outputs of the booster together into a single output and then outputting the single output, wherein each of the boosters starts MPPT operation, which operates so that the output power of the solar cells is controlled so as to reach a maximum value, with different periods.

摘要翻译： 电流收集箱包括：串联连接多个太阳能电池组的至少两个太阳能电池串的多个端子; 用于升压通过端子输入的每个太阳能电池串的发电功率的单独电压的升压器; 以及输出电路，用于将所述升压器的所有输出一起汇集成单个输出，然后输出单个输出，其中每个升压器开始MPPT操作，其操作使得太阳能电池的输出功率被控制为 达到最大值，具有不同的周期。