公开(公告)号：US08592296B2

公开(公告)日：2013-11-26

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L21/3205

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US08786030B2

公开(公告)日：2014-07-22

申请号：US13570388

申请日：2012-08-09

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L21/02

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US20120299123A1

公开(公告)日：2012-11-29

申请号：US13570388

申请日：2012-08-09

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US20110309455A1

公开(公告)日：2011-12-22

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US08941184B2

公开(公告)日：2015-01-27

申请号：US13327870

申请日：2011-12-16

申请人： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.

摘要翻译： 一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。 还公开了制造半导体器件的方法，其包括栅极最后工艺。

公开(公告)号：US20090108294A1

公开(公告)日：2009-04-30

申请号：US11928391

申请日：2007-10-30

申请人： Changhwan Choi ,  Takashi Ando ,  Kisik Choi ,  Vijay Narayanan

发明人： Changhwan Choi ,  Takashi Ando ,  Kisik Choi ,  Vijay Narayanan

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/66545

摘要： A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g., at about 1,000° C. so that the materials in the stack are mixed to form a mixed high-k gate dielectric layer. The mixed high-k gate dielectric layer is doped with a group IIA/IIIB element and aluminum, and has a lower effective oxide thickness (EOT) than a conventional gate stack containing no aluminum. The inventive mixed high-k gate dielectric layer is amenable to EOT scaling due to the absence of a dielectric interface layer, which is caused by scavenging, i.e. consumption of any dielectric interface layer, by the IIA/IIB elements and aluminum.

摘要翻译： 在半导体衬底上依次形成包括电介质界面层，高k栅极电介质层，IIA / IIIB族元素层的叠层。 在叠层上形成金属氮化铝层和任选的半导体层。 堆叠在升高的温度例如约1000℃下退火，使得堆叠中的材料被混合以形成混合的高k栅极电介质层。 混合的高k栅极电介质层掺杂有IIA / IIIB族元素和铝，并且具有比不含铝的常规栅极叠层更低的有效氧化物厚度（EOT）。 本发明的混合高k栅极电介质层由于不存在由IIA / IIB元素和铝的清除即任何介电界面层的消耗而引起的电介质界面层，因此易于进行EOT缩放。

公开(公告)号：US20130154019A1

公开(公告)日：2013-06-20

申请号：US13327870

申请日：2011-12-16

申请人： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.

摘要翻译： 一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。 还公开了制造半导体器件的方法，其包括栅极最后工艺。

公开(公告)号：US20130095629A1

公开(公告)日：2013-04-18

申请号：US13617426

申请日：2012-09-14

申请人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/66803 ,  H01L29/785

摘要： Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.

摘要翻译： 公开了通过在源极区域和漏极区域之间在衬底上形成至少一个导电沟道来制造晶体管，例如FinFET的方法; 形成栅极结构以设置在所述沟道的一部分上，所述栅极结构具有限定所述栅极结构的两个相对侧壁的宽度和长度以及高度，并且形成为使得所述沟道穿过所述侧壁; 在侧壁上形成间隔物; 在所述通道上形成外延硅层; 去除垫片; 以及形成电介质层，以设置在所述栅极结构和所述沟道结构的外部的部分上，使得电容减小气隙位于所述电介质层的下面，并且在所述栅极结构的侧壁附近设置在区域 以前被隔离物占据。

公开(公告)号：US20130161763A1

公开(公告)日：2013-06-27

申请号：US13332991

申请日：2011-12-21

申请人： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

发明人： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78621

摘要： A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.

摘要翻译： 一种方法包括在半导体的表面上形成由插头构成的虚拟栅极结构; 形成围绕所述插塞的第一间隔件，所述第一间隔件是牺牲间隔件; 以及执行成角度的离子注入，以便将掺杂剂物质注入与所述第一间隔物的外侧壁相邻的所述半导体的表面中，以形成源延伸区域和漏极延伸区域，其中所述注入的掺杂剂物质在所述外侧壁 的第一间隔物的量是离子注入的角度的函数。 该方法还包括执行激光退火以激活源延伸和漏极延伸植入。 该方法还包括形成围绕第一间隔件的第二间隔件，去除第一间隔件和插塞以形成开口，以及在开口中沉积栅极堆叠。

公开(公告)号：US08637930B2

公开(公告)日：2014-01-28

申请号：US13272409

申请日：2011-10-13

申请人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66803 ,  H01L29/785

摘要： A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.

摘要翻译： 晶体管，例如FinFET，包括设置在衬底上的栅极结构。 栅极结构具有宽度以及限定栅极结构的两个相对侧壁的长度和高度。 晶体管还包括通过栅极结构的侧壁的源极区域和漏极区域之间的至少一个导电沟道; 设置在所述栅极结构上方的电介质层和在所述栅极结构外部的所述导电沟道的部分; 以及介电层下面的气隙。 气隙设置成与栅极结构的侧壁相邻，并且用于减小晶体管的寄生电容。 还公开了制造晶体管的至少一种方法。