公开(公告)号：US11263012B2

公开(公告)日：2022-03-01

申请号：US16735564

申请日：2020-01-06

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US20170293539A1

公开(公告)日：2017-10-12

申请号：US15632567

申请日：2017-06-26

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/20 ,  G06F9/30 ,  G06F3/06

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US20140143580A1

公开(公告)日：2014-05-22

申请号：US13679690

申请日：2012-11-16

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Ali Vahidsafa

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat.

Abstract translation: 本公开的实现涉及用于将至少一个新激活的处理器与至少一个先前运行的处理器同步的装置和/或方法。 每个处理器配置为产生心跳并根据STICK进行操作。 当添加先前停用的处理器时，每个活动处理器的心跳被复位，并且当前的STICK在下一个心跳上传输到新激活的处理器。 然后，新激活的处理器可以将心跳周期添加到所获取的STICK，并且在下一个心跳之后开始递增STICK和正常操作。

公开(公告)号：US20140136912A1

公开(公告)日：2014-05-15

申请号：US13673503

申请日：2012-11-09

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Robert P. Masleid ,  Ali Vahidsafa

IPC: G01R31/3177

CPC classification number: G01R31/318541

Abstract: A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit.

Abstract translation: 具有扫描电路的组合动态触发器包括触发器电路，扫描控制电路和输出缓冲电路。 触发器电路包括动态锁存电路和静态锁存电路。 动态锁存电路包括动态锁存存储节点。 静态锁存电路包括由动态锁存器驱动的静态存储节点。 扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。 扫描锁存电路包括扫描反馈电路，扫描存储节点和从静态锁存器驱动的扫描前馈电路。 输出缓冲电路包括从动态锁存电路驱动的动态锁存驱动器和从静态锁存电路驱动的静态驱动器。

公开(公告)号：US10467139B2

公开(公告)日：2019-11-05

申请号：US15859037

申请日：2017-12-29

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Damien Walker ,  Priyambada Mitra ,  Ali Vahidsafa ,  Matthew Cohen ,  Josephus Ebergen ,  Andrew Brock

IPC: G06F12/0817 ,  G06F12/0813 ,  G06F12/0842

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.

公开(公告)号：US10452547B2

公开(公告)日：2019-10-22

申请号：US15858787

申请日：2017-12-29

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Damien Walker ,  Priyambada Mitra ,  Ali Vahidsafa ,  Matthew Cohen ,  Josephus Ebergen ,  Andrew Brock

IPC: G06F12/00 ,  G06F12/0817 ,  G06F12/128 ,  G06F12/0813

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.

公开(公告)号：US10248520B2

公开(公告)日：2019-04-02

申请号：US15202308

申请日：2016-07-05

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F11/00 ,  G06F11/25

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting an at-speed functional test on a silicon wafer of an integrated circuit. In one embodiment, the method includes utilizing a first clock signal during a first portion of the test and a second clock signal during a second portion. The clock signals are configured such that a first subset of the logic stages of the circuit are tested at-speed by the first portion and a second subset of the logic stages of the circuit are tested at-speed. Further, in one embodiment, the first subset and the second subset comprise all of the logic stages of the circuit design. Through the configuration of the clock signals, the tester may ensure that each stage of the circuit design is tested at-speed such that a more accurate at-speed test result may be obtained in a low current environment.

公开(公告)号：US10007629B2

公开(公告)日：2018-06-26

申请号：US14598640

申请日：2015-01-16

Applicant: Oracle International Corporation

Inventor： Thomas Wicki ,  David Smentek ,  Sumti Jairath ,  Kathirgamar Aingaran ,  Ali Vahidsafa ,  Paul Loewenstein

IPC: G06F11/00 ,  G06F13/40 ,  G06F11/30 ,  G06F11/22

CPC classification number: G06F13/4022 ,  G06F11/221 ,  H04L12/00 ,  H04L12/4625

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

公开(公告)号：US09710273B2

公开(公告)日：2017-07-18

申请号：US14549742

申请日：2014-11-21

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/00 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30145 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/2028 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/13

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US09632141B2

公开(公告)日：2017-04-25

申请号：US14316468

申请日：2014-06-26

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Roger Charles Mistely

IPC: G01R31/3185 ,  G01R31/319 ,  G06F11/22

CPC classification number: G01R31/31922 ,  G01R31/318552 ,  G01R31/318563 ,  G01R31/318594 ,  G01R31/31908 ,  G06F11/2236 ,  G06F11/263

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.