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    Device and method for thermally treating semiconductor wafers
    3.
    发明申请
    Device and method for thermally treating semiconductor wafers 有权
    用于热处理半导体晶片的装置和方法

    公开(公告)号：US20060105584A1

    公开(公告)日：2006-05-18

    申请号：US10524871

    申请日：2003-07-25

    申请人： Georg Roters ,  Steffen Frigge ,  Sing Tay ,  Yao Zhi Hu ,  Regina Hayn ,  Jens-Uwe Sachse ,  Erwin Schoer ,  Wilhelm Kegel

    发明人： Georg Roters ,  Steffen Frigge ,  Sing Tay ,  Yao Zhi Hu ,  Regina Hayn ,  Jens-Uwe Sachse ,  Erwin Schoer ,  Wilhelm Kegel

    IPC分类号： H01L21/324

    CPC分类号： H01L21/67115 ,  H01L21/28247 ,  H01L21/32105

    摘要： A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.

    摘要翻译： 一种用于热处理半导体晶片的装置，其具有至少一个待氧化的硅层和不被氧化的金属层，优选钨层。 本发明的装置包括：至少一个辐射源; 接收衬底的处理室，其中至少一个壁部分位于辐射源附近，并且对于所述辐射源的辐射基本上是透明的; 以及至少一个覆盖板，位于基板与位于辐射源附近的处理室的壁部分之间，所述盖板的尺寸被选择为使得其相对于基板完全覆盖处理室的透明壁部分 为了防止包含来自所述衬底的金属，金属氧化物或金属氢氧化物如钨，氧化钨或氢氧化钨的材料沉积在或蒸发到处理室的透明壁部分上。

    Semiconductor memory with vertical charge-trapping memory cells and fabrication
    5.
    发明申请
    Semiconductor memory with vertical charge-trapping memory cells and fabrication 审中-公开
    具有垂直电荷捕获存储单元和制造的半导体存储器

    公开(公告)号：US20060065922A1

    公开(公告)日：2006-03-30

    申请号：US11272637

    申请日：2005-11-14

    申请人： Christoph Kleint ,  Joachim Deppe ,  Christoph Ludwig ,  Jens-Uwe Sachse

    发明人： Christoph Kleint ,  Joachim Deppe ,  Christoph Ludwig ,  Jens-Uwe Sachse

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833

    摘要： A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.

    摘要翻译： 半导体器件通过在半导体本体中形成多个沟槽而形成。 沟槽在有源沟槽和隔离沟槽之间交替，隔离沟槽比有源沟槽更深。 半导体本体被掺杂，使得与每个有源沟槽相邻的半导体本体的顶表面和每个有源沟槽的底板被掺杂。 在每个有源沟槽中形成存储单元元件。 存储单元部件包括设置在栅电极和沟槽的侧壁之间的栅电极和电荷捕获层。 电荷捕获层包括设置在第一和第二限制层之间的存储层。 位线形成在半导体主体上并与邻近有源沟槽的半导体本体的顶表面相邻的电耦合掺杂区。 位线触点耦合到位线。

    Semiconductor memory with vertical charge-trapping memory cells and fabrication
    6.
    发明授权
    Semiconductor memory with vertical charge-trapping memory cells and fabrication 失效
    具有垂直电荷捕获存储单元和制造的半导体存储器

    公开(公告)号：US06992348B2

    公开(公告)日：2006-01-31

    申请号：US10741970

    申请日：2003-12-19

    申请人： Christoph Kleint ,  Joachim Deppe ,  Christoph Ludwig ,  Jens-Uwe Sachse

    发明人： Christoph Kleint ,  Joachim Deppe ,  Christoph Ludwig ,  Jens-Uwe Sachse

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L29/66833

    摘要： Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

    摘要翻译： 在存储单元场之外，在顶位线上提供位线触点，并且在下位线上提供额外的位线触点，并且各自以导电方式连接到为布线提供的金属化层。 用于高位线的位线触点和用于低位线的附加位线触点形成在存储器单元场的相对侧上，并且隔离沟槽的部分存在于附加位线触点之间。