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    Method for fabricating semiconductor memories with charge trapping memory cells
    9.
    发明授权
    Method for fabricating semiconductor memories with charge trapping memory cells 失效
    用电荷俘获存储单元制造半导体存储器的方法

    公开(公告)号：US07005355B2

    公开(公告)日：2006-02-28

    申请号：US10735411

    申请日：2003-12-12

    申请人： Christoph Kleint ,  Christoph Ludwig ,  Joachim Deppe ,  Jens-Uwe Sachse

    发明人： Christoph Kleint ,  Christoph Ludwig ,  Joachim Deppe ,  Jens-Uwe Sachse

    IPC分类号： H01L21/74 ,  H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

    摘要翻译： 一种制造半导体器件的方法包括：在半导体本体上形成存储层。 存储层包括第一边界层，中间存储层和第二边界层。 存储层被图案化，使得存储层中的至少一些从半导体主体的第一部分上方移除，并且存储层中的一些从半导体本体的第二部分上移除。 半导体本体的第一部分被掺杂，半导体本体的第二部分被蚀刻。

    Semiconductor memory with vertical charge-trapping memory cells and fabrication
    10.
    发明申请
    Semiconductor memory with vertical charge-trapping memory cells and fabrication 审中-公开
    具有垂直电荷捕获存储单元和制造的半导体存储器

    公开(公告)号：US20060065922A1

    公开(公告)日：2006-03-30

    申请号：US11272637

    申请日：2005-11-14

    申请人： Christoph Kleint ,  Joachim Deppe ,  Christoph Ludwig ,  Jens-Uwe Sachse

    发明人： Christoph Kleint ,  Joachim Deppe ,  Christoph Ludwig ,  Jens-Uwe Sachse

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833

    摘要： A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.

    摘要翻译： 半导体器件通过在半导体本体中形成多个沟槽而形成。 沟槽在有源沟槽和隔离沟槽之间交替，隔离沟槽比有源沟槽更深。 半导体本体被掺杂，使得与每个有源沟槽相邻的半导体本体的顶表面和每个有源沟槽的底板被掺杂。 在每个有源沟槽中形成存储单元元件。 存储单元部件包括设置在栅电极和沟槽的侧壁之间的栅电极和电荷捕获层。 电荷捕获层包括设置在第一和第二限制层之间的存储层。 位线形成在半导体主体上并与邻近有源沟槽的半导体本体的顶表面相邻的电耦合掺杂区。 位线触点耦合到位线。