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公开(公告)号：US20230274864A1
公开(公告)日：2023-08-31
申请号：US18173598
申请日：2023-02-23
Inventor： Yuto AKIYAMA , Ken YANAI , Masashi TAKAMURA , Yuji YAMAGISHI , Ryosuke USUI
Abstract: A multilayer varistor according to the present disclosure includes: a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion. The first high-resistivity layer has a larger average thickness than the second high-resistivity layer.
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公开(公告)号：US20240312677A1
公开(公告)日：2024-09-19
申请号：US18263647
申请日：2022-02-08
Inventor： Masaya HATTORI , Takeshi FUJII , Yasuhiko SASAKI , Yoshiyuki SAITO , Tomohide KAMIYAMA , Ken YANAI
Abstract: A varistor component includes: a varistor-material sintered body; a first external electrode provided on a portion of a first lateral surface; a second external electrode provided on a portion of the first lateral surface; and a third external electrode provided on a portion of a second lateral surface. The first external electrode, the second external electrode, and the third external electrode are not provided on a third lateral surface or a fourth lateral surface. The first external electrode and the second external electrode are spaced apart from each other in a first direction on the first lateral surface. The third external electrode provided on the second lateral surface is located between the first external electrode and the second external electrode, when viewed in a second direction.
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公开(公告)号：US20220310291A1
公开(公告)日：2022-09-29
申请号：US17838961
申请日：2022-06-13
Inventor： Ken YANAI , Tomokazu YAMAGUCHI , Yuji YAMAGISHI , Naoki MUTOU , Sayaka MATSUMOTO , Ryosuke USUI
Abstract: A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.
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公开(公告)号：US20240105365A1
公开(公告)日：2024-03-28
申请号：US18264034
申请日：2022-02-18
Inventor： Yuto AKIYAMA , Masashi TAKAMURA , Ken YANAI
Abstract: An object of the present disclosure is to provide a multilayer varistor with the ability to reduce the chances of causing crosstalk between external terminals. Inside a sintered body having the shape of a rectangular parallelepiped, of which the longitudinal axis is aligned with a first direction, a first facing portion and a second facing portion are provided to interpose a third facing portion between themselves. At least one of a first side surface or a second side surface is provided with a first external electrode connected to the first facing portion, a second external electrode connected to the second facing portion, and a third external electrode and a fourth external electrode connected to the third facing portion. In the first direction, the first external electrode and the second external electrode are interposed between the third external electrode and the fourth external electrode.
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公开(公告)号：US20230245806A1
公开(公告)日：2023-08-03
申请号：US18098998
申请日：2023-01-19
Inventor： Naoki MUTOU , Yoshiyuki SATOU , Yuji YAMAGISHI , Ken YANAI
IPC: H01C7/112 , H01C7/18 , C04B35/453 , C04B35/64
CPC classification number: H01C7/112 , C04B35/64 , C04B35/453 , H01C7/18
Abstract: A method for manufacturing a multilayer varistor includes: a first step including providing a multilayer stack in which a plurality of green sheet layers, each containing a Zn oxide powder as a main component and a Pr oxide powder as a sub-component, and a plurality of internal electrode paste layers, each containing a Pd powder, are alternately stacked; and a second step including forming a sintered compact, including an internal electrode inside, by baking the multilayer stack. The second step includes: a first sub-step including baking the multilayer stack by setting an oxygen concentration in an atmosphere at 1000 ppm by volume or less while increasing a temperature from 500° C. to 800° C.; and a second sub-step including baking, after the first sub-step, the multilayer stack by setting the oxygen concentration in the atmosphere at 1000 ppm by volume or more while increasing the temperature to a maximum allowable temperature.
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Patent Agency Ranking
公开(公告)号：US20230326636A1
公开(公告)日：2023-10-12
申请号：US18182134
申请日：2023-03-10
Inventor： Masashi TAKAMURA , Yuto AKIYAMA , Ken YANAI
CPC classification number: H01C7/1006 , H01C1/14 , H01C7/102 , H01C7/112
Abstract: A multilayer varistor includes a sintered body and a first internal electrode, a second internal electrode, a third internal electrode, and a fourth internal electrode which are disposed in the sintered body. The first internal electrode, the second internal electrode, the third internal electrode, and the fourth internal electrode are arranged in an order of the first internal electrode, the third internal electrode, the fourth internal electrode, and the second internal electrode from a side of a first main face. The third internal electrode and the fourth internal electrode are electrically connected to each other. At least part of the first internal electrode and at least part of the third internal electrode overlap each other when viewed in a third direction. At least part of the second internal electrode and at least part of the fourth internal electrode overlap each other when viewed in the third direction.
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公开(公告)号：US20230274863A1
公开(公告)日：2023-08-31
申请号：US18173584
申请日：2023-02-23
Inventor： Yuto AKIYAMA , Ken YANAI , Ryosuke USUI , Yuji YAMAGISHI , Masashi TAKAMURA
Abstract: A multilayer varistor according to the present disclosure includes; a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes a thinner region having a smaller thickness than a surrounding region that surrounds the thinner region.
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公开(公告)号：US20230207159A1
公开(公告)日：2023-06-29
申请号：US18068282
申请日：2022-12-19
Inventor： Yuto AKIYAMA , Ken YANAI , Ryosuke USUI , Yuji YAMAGISHI
Abstract: A multilayer varistor includes: a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially and containing element Si; and an external electrode arranged to cover the high-resistivity layer partially, electrically connected to the internal electrode, and containing silver as a main component thereof. A ratio of a total mass of the alkali metals and the alkaline earth metals to a mass of the element Si in a surface region of the high-resistivity layer is equal to or less than 0.6.
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公开(公告)号：US20250087393A1
公开(公告)日：2025-03-13
申请号：US18957218
申请日：2024-11-22
Inventor： Masashi TAKAMURA , Ken YANAI , Sayaka WATANABE , Tomomitsu MURAISHI
Abstract: A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.
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公开(公告)号：US20230197321A1
公开(公告)日：2023-06-22
申请号：US18064650
申请日：2022-12-12
Inventor： Yuto AKIYAMA , Ryosuke USUI , Ken YANAI
Abstract: A multilayer varistor of the present disclosure includes a sintered body, a first internal electrode, a second internal electrode, a first external electrode, a second external electrode, and a high-resistance layer. The first internal electrode and the second internal electrode are disposed in the sintered body. The first external electrode is disposed on a surface of the sintered body and is electrically connected to the first internal electrode. The second external electrode is disposed on the surface of the sintered body and is electrically connected to the second internal electrode. The high-resistance layer covers at least part of the surface of the sintered body, and the high-resistance layer has a surface having a plurality of cracks.
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