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公开(公告)号：US08592932B2
公开(公告)日：2013-11-26
申请号：US13430195
申请日：2012-03-26
IPC分类号： H01L31/0203
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
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2.发明申请Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers 审中-公开使用硅空间变压器载体构建半导体芯片封装的装置和方法公开(公告)号：US20080284037A1
公开(公告)日：2008-11-20
申请号：US11748818
申请日：2007-05-15
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。
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3.发明授权Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers 失效用硅空间变压器承载构造半导体芯片封装的装置和方法公开(公告)号：US08012796B2
公开(公告)日：2011-09-06
申请号：US12538223
申请日：2009-08-10
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。
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4.发明申请APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS 审中-公开用硅空间变压器构造半导体芯片包装的装置和方法公开(公告)号：US20100013073A1
公开(公告)日：2010-01-21
申请号：US12543827
申请日：2009-08-19
IPC分类号： H01L23/52
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。
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5.发明申请公开(公告)号：US20090311828A1
公开(公告)日：2009-12-17
申请号：US12538223
申请日：2009-08-10
IPC分类号： H01L21/768 , H01L21/50
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。
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6.发明授权Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers 有权用硅空间变压器承载构造半导体芯片封装的装置和方法公开(公告)号：US09159602B2
公开(公告)日：2015-10-13
申请号：US12543827
申请日：2009-08-19
IPC分类号： H01L23/02 , H01L21/683 , H01L23/14 , H01L23/498 , H01L23/50 , H01L23/00 , H01L25/065
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。
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7.发明申请公开(公告)号：US20120181648A1
公开(公告)日：2012-07-19
申请号：US13430195
申请日：2012-03-26
IPC分类号： H01L23/48 , H01L31/0232
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。
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8.发明授权Structure and method for creating reliable deep via connections in a silicon carrier 有权用于在硅载体中创建可靠的深通孔连接的结构和方法公开(公告)号：US08080876B2
公开(公告)日：2011-12-20
申请号：US12147466
申请日：2008-06-26
IPC分类号： H01L23/538
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。
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9.发明申请STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER 有权通过硅载体连接创造可靠深度的结构和方法公开(公告)号：US20090039472A1
公开(公告)日：2009-02-12
申请号：US12147466
申请日：2008-06-26
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。
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10.发明申请STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER 审中-公开通过硅载体连接创造可靠深度的结构和方法公开(公告)号：US20080179755A1
公开(公告)日：2008-07-31
申请号：US11669924
申请日：2007-01-31
申请人： Paul S. Andry , L. Paivikki Buchwalter , Anurag Jain , John U. Knickerbocker , Edmund J. Sprogis , Michelle L. Steen , Cornelia K. Tsang
发明人： Paul S. Andry , L. Paivikki Buchwalter , Anurag Jain , John U. Knickerbocker , Edmund J. Sprogis , Michelle L. Steen , Cornelia K. Tsang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。
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