公开(公告)号：US08778737B2

公开(公告)日：2014-07-15

申请号：US13285443

申请日：2011-10-31

Applicant: Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/00 ,  H01L29/10

CPC classification number: H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract translation: 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US08440544B2

公开(公告)日：2013-05-14

申请号：US12899127

申请日：2010-10-06

Applicant: Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/301

CPC classification number: H01L29/06 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.

Abstract translation: 具有替代衬底的CMOS结构和制造方法在本文中公开。 该方法包括在临时衬底上形成器件。 该方法还包括移除临时衬底。 所述方法还包括用固定结构将永久电绝缘衬底粘合到所述器件上。

公开(公告)号：US08263497B2

公开(公告)日：2012-09-11

申请号：US12352718

申请日：2009-01-13

Applicant: Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

Abstract translation: 获得包括具有前侧和后侧的主体的主晶片和终止于背面的多个盲电通路的组件和处理器晶片。 一个步骤包括将盲电通孔暴露在背面的各种高度上。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 并向后侧施加第二化学机械抛光工艺。

公开(公告)号：US20110290402A1

公开(公告)日：2011-12-01

申请号：US12788832

申请日：2010-05-27

Applicant: Paul Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

Inventor： Paul Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC: B32B33/00 ,  B29C65/16

CPC classification number: H01L21/67132 ,  C09J5/06 ,  C09J2203/326 ,  C09J2479/08 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68381 ,  Y10T156/1158

Abstract: A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.

Abstract translation: 一种用于将处理器附接到晶片的方法，所述晶片包括集成电路（IC），包括在所述晶片上形成粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，所述聚酰亚胺基聚合物构造成经受超过约280℃的温度下的加工 C。; 以及使用所述粘合剂层将处理器粘附到所述晶片。 一种用于将处理器附接到晶片的系统，包括IC的晶片包括位于晶片上的粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，其被配置为经受超过约280℃的温度下的加工; 以及使用粘合剂层粘附到晶片的处理器。

公开(公告)号：US20110037161A1

公开(公告)日：2011-02-17

申请号：US12540510

申请日：2009-08-13

Applicant: Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC: H01L23/488 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

Abstract translation: 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US07791168B2

公开(公告)日：2010-09-07

申请号：US11930698

申请日：2007-10-31

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L29/00 ,  H01L23/52 ,  H01L23/04 ,  H01L23/053

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其中包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US07691669B2

公开(公告)日：2010-04-06

申请号：US12056852

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/8242

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US07488624B2

公开(公告)日：2009-02-10

申请号：US12056808

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/82

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US07435627B2

公开(公告)日：2008-10-14

申请号：US11201572

申请日：2005-08-11

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/82

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20080182359A1

公开(公告)日：2008-07-31

申请号：US12056852

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/00

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。