公开(公告)号：US09293535B2

公开(公告)日：2016-03-22

申请号：US13610901

申请日：2012-09-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7815

摘要： A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

摘要翻译： 功率MOSFET具有主FET（MFET）和嵌入式电流感测FET（SFET）。 MFET栅极流道通过MFET和SFET之间的缓冲空间中的隔离栅极流道（IGR）耦合到SFET栅极流道。 在一个实施例中，n IGR（i = 1至n）将MFET（304）的第一部分的n + 1个栅极耦合到SFET的n个栅极。 IGR具有曲折的中心部分，其中每个SFET栅极流道经由IGR耦合到两个MFET栅极流道。 曲折的中心部分提供阻挡除了第一和最后一次IGR的外侧之外的所有IGR的SFET源和MFET源之间的寄生泄漏路径。 这些可能通过在围绕剩余泄漏路径的区域中增加体掺杂来阻止。 IGR基本上没有源区。

公开(公告)号：US20140070313A1

公开(公告)日：2014-03-13

申请号：US13610901

申请日：2012-09-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7815

摘要： A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

摘要翻译： 功率MOSFET具有主FET（MFET）和嵌入式电流感测FET（SFET）。 MFET栅极流道通过MFET和SFET之间的缓冲空间中的隔离栅极流道（IGR）耦合到SFET栅极流道。 在一个实施例中，n IGR（i = 1至n）将MFET（304）的第一部分的n + 1个栅极耦合到SFET的n个栅极。 IGR具有曲折的中心部分，其中每个SFET栅极流道经由IGR耦合到两个MFET栅极流道。 曲折的中心部分提供阻挡除了第一和最后一次IGR的外侧之外的所有IGR的SFET源和MFET源之间的寄生泄漏路径。 这些可能通过在围绕剩余泄漏路径的区域中增加体掺杂来阻止。 IGRs基本上没有源区。

公开(公告)号：US08143126B2

公开(公告)日：2012-03-27

申请号：US12777066

申请日：2010-05-10

申请人： Jingjing Chen ,  Ganming Qin ,  Edouard D. de Fresart ,  Pon Sung Ku

发明人： Jingjing Chen ,  Ganming Qin ,  Edouard D. de Fresart ,  Pon Sung Ku

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42376 ,  H01L29/66734

摘要： A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.

摘要翻译： 使用一种方法来形成垂直MOS晶体管。 该方法利用半导体层。 在半导体层中蚀刻开口。 栅极电介质形成在开口中，其具有延伸到第一半导体层的顶表面的垂直部分。 栅极形成在开口中，其主要部分横向邻近栅极电介质的垂直部分，并且悬垂部分横向延伸越过栅极电介质的垂直部分。 执行注入以在半导体层的顶表面处形成源极区域，同时存在突出部分。

公开(公告)号：US20110275187A1

公开(公告)日：2011-11-10

申请号：US12777066

申请日：2010-05-10

申请人： Jingjing Chen ,  Ganming Qin ,  Edouard D. de Fresart ,  Pon Sung Ku

发明人： Jingjing Chen ,  Ganming Qin ,  Edouard D. de Fresart ,  Pon Sung Ku

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42376 ,  H01L29/66734

摘要： A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.

摘要翻译： 使用一种方法来形成垂直MOS晶体管。 该方法利用半导体层。 在半导体层中蚀刻开口。 栅极电介质形成在开口中，其具有延伸到第一半导体层的顶表面的垂直部分。 栅极形成在开口中，其主要部分横向邻近栅极电介质的垂直部分，并且悬垂部分横向延伸越过栅极电介质的垂直部分。 执行注入以在半导体层的顶表面处形成源极区域，同时存在突出部分。

公开(公告)号：US09178027B1

公开(公告)日：2015-11-03

申请号：US14457824

申请日：2014-08-12

申请人： Moaniss Zitouni ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

摘要翻译： 一种器件包括具有表面的半导体衬底，半导体衬底中的从表面垂直延伸的沟槽，与沟槽横向相邻的主体区域，与表面间隔开，具有第一导电类型，并且其中在操作期间形成沟道 ，在身体区域和表面之间的漂移区域，并且具有第二导电类型，施加设置在与身体区域相邻的沟槽中的栅极结构，从表面凹陷并被配置为接收控制电压以控制形成 沟道，以及沿栅极结构和主体区域之间的沟槽的侧壁设置的栅极电介质层。 栅极结构和栅极电介质层与漂移区域具有实质的垂直重叠，使得通过施加控制电压来减小漂移区域中的电场幅度。

公开(公告)号：US20090108339A1

公开(公告)日：2009-04-30

申请号：US11932070

申请日：2007-10-31

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Ganming Qin ,  Hongwei Zhou

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Ganming Qin ,  Hongwei Zhou

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719

摘要： A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

摘要翻译： 使用第一类型的半导体层（16）形成TMOS器件（10）。 第二类型的第一和第二区域（62,64）形成在半导体层中并且间隔开。 通过注入在半导体层中形成第三区域（68）。 第三区域在第一和第二掺杂区域之间并且与第一和第二掺杂区域接触，具有第二导电类型，并且比第一和第二掺杂区域重掺杂。 栅极堆叠（67）形成在第一掺杂区域的一部分，第二掺杂区域的一部分和第三掺杂区域上。 通过在形成栅叠层之后注入，第一类型的第四和第五区（98,100）分别形成在第一和第二掺杂区的内部。 与第一和第二区域具有相同导电类型的第三区域减小了米勒电容。

公开(公告)号：US20160049508A1

公开(公告)日：2016-02-18

申请号：US14926288

申请日：2015-10-29

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

摘要翻译： 一种器件包括具有表面的半导体衬底，半导体衬底中的从表面垂直延伸的沟槽，与沟槽横向相邻的主体区域，与表面间隔开，具有第一导电类型，并且其中在操作期间形成沟道 ，在身体区域和表面之间的漂移区域，并且具有第二导电类型，施加设置在与身体区域相邻的沟槽中的栅极结构，从表面凹陷并被配置为接收控制电压以控制形成 沟道，以及沿栅极结构和主体区域之间的沟槽的侧壁设置的栅极电介质层。 栅极结构和栅极电介质层与漂移区域具有实质的垂直重叠，使得通过施加控制电压来减小漂移区域中的电场幅度。

公开(公告)号：US09419128B2

公开(公告)日：2016-08-16

申请号：US14926288

申请日：2015-10-29

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

公开(公告)号：US09362394B2

公开(公告)日：2016-06-07

申请号：US14307678

申请日：2014-06-18

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Ganming Qin

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Ganming Qin

IPC分类号： H01L29/78 ,  G06F17/50 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/7813 ,  G06F17/5009 ,  G06F17/5072 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

摘要翻译： 本文公开了功率器件端接结构和方法。 该结构包括沟槽栅极半导体器件。 沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。 阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。 内部晶体管包括具有平均内部区域间隔的多个内部沟槽。 外部晶体管包括具有平均端接区域间隔的多个外部沟槽。 平均端接区域间隔大于平均内部区域间隔，或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。

公开(公告)号：US20150372130A1

公开(公告)日：2015-12-24

申请号：US14307678

申请日：2014-06-18

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Ganming Qin

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Ganming Qin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  G06F17/50 ,  H01L29/40

CPC分类号： H01L29/7813 ,  G06F17/5009 ,  G06F17/5072 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

摘要翻译： 本文公开了功率器件端接结构和方法。 该结构包括沟槽栅极半导体器件。 沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。 阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。 内部晶体管包括具有平均内部区域间隔的多个内部沟槽。 外部晶体管包括具有平均端接区域间隔的多个外部沟槽。 平均端接区域间隔大于平均内部区域间隔，或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。