公开(公告)号：US20160049508A1

公开(公告)日：2016-02-18

申请号：US14926288

申请日：2015-10-29

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

摘要翻译： 一种器件包括具有表面的半导体衬底，半导体衬底中的从表面垂直延伸的沟槽，与沟槽横向相邻的主体区域，与表面间隔开，具有第一导电类型，并且其中在操作期间形成沟道 ，在身体区域和表面之间的漂移区域，并且具有第二导电类型，施加设置在与身体区域相邻的沟槽中的栅极结构，从表面凹陷并被配置为接收控制电压以控制形成 沟道，以及沿栅极结构和主体区域之间的沟槽的侧壁设置的栅极电介质层。 栅极结构和栅极电介质层与漂移区域具有实质的垂直重叠，使得通过施加控制电压来减小漂移区域中的电场幅度。

公开(公告)号：US09419128B2

公开(公告)日：2016-08-16

申请号：US14926288

申请日：2015-10-29

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

公开(公告)号：US09178027B1

公开(公告)日：2015-11-03

申请号：US14457824

申请日：2014-08-12

申请人： Moaniss Zitouni ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

摘要翻译： 一种器件包括具有表面的半导体衬底，半导体衬底中的从表面垂直延伸的沟槽，与沟槽横向相邻的主体区域，与表面间隔开，具有第一导电类型，并且其中在操作期间形成沟道 ，在身体区域和表面之间的漂移区域，并且具有第二导电类型，施加设置在与身体区域相邻的沟槽中的栅极结构，从表面凹陷并被配置为接收控制电压以控制形成 沟道，以及沿栅极结构和主体区域之间的沟槽的侧壁设置的栅极电介质层。 栅极结构和栅极电介质层与漂移区域具有实质的垂直重叠，使得通过施加控制电压来减小漂移区域中的电场幅度。

公开(公告)号：US06448625B1

公开(公告)日：2002-09-10

申请号：US09808966

申请日：2001-03-16

申请人： Zia Hossain ,  Evgueniy N. Stefanov ,  Mohammed Tanvir Quddus ,  Joe Fulton ,  Mohamed Imam

发明人： Zia Hossain ,  Evgueniy N. Stefanov ,  Mohammed Tanvir Quddus ,  Joe Fulton ,  Mohamed Imam

IPC分类号： H01L2358

CPC分类号： H01L29/66659 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/7835

摘要： A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

摘要翻译： 公开了一种高压MOS器件（100）。 MOS器件包括具有两个区域的n阱区域（113）。 第一区域（110）具有高掺杂剂浓度，第二区域（112）具有低掺杂剂浓度。 在阱区内部形成二次导电型（108）的区域。 第二区域（110）通常位于门（105）下方。 当器件处于“导通”状态时，该器件阻塞电压时，该区域中较低的掺杂浓度有助于提高击穿电压，有助于降低导通电阻。

公开(公告)号：US06492679B1

公开(公告)日：2002-12-10

申请号：US09920655

申请日：2001-08-03

申请人： Mohamed Imam ,  Joe Fulton ,  Zia Hossain ,  Masami Tanaka ,  Taku Yamamoto ,  Yoshio Enosawa ,  Katsuya Yamazaki ,  Evgueniy N. Stefanov

发明人： Mohamed Imam ,  Joe Fulton ,  Zia Hossain ,  Masami Tanaka ,  Taku Yamamoto ,  Yoshio Enosawa ,  Katsuya Yamazaki ,  Evgueniy N. Stefanov

IPC分类号： H01L2976

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/7835

摘要： A high voltage MOSFET device (100) has a well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate region (105). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the “on” state. The MOSFET device further has a p-top layer (108) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.

摘要翻译： 高电压MOSFET器件（100）具有带有两个区域的阱区（113）。 第一区域（110）具有高掺杂剂浓度，第二区域（112）具有低掺杂剂浓度。 在阱区内形成二次导电型（108）的区域。 第二区域（110）通常位于栅极区域（105）下方。 当半导体器件处于“导通”状态时，该半导体器件阻挡电压并有助于降低导通电阻，该区域中较低的掺杂浓度有助于提高击穿电压。 MOSFET器件还具有p顶层（108），其设置在阱区的顶表面上，然后通过在惰性气氛中的高温退火MOSFET器件而被驱动进入阱区。