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    Standard cell architecture for gate tie-off
    3.
    发明授权
    Standard cell architecture for gate tie-off 有权

    公开(公告)号：US10600866B2

    公开(公告)日：2020-03-24

    申请号：US15886611

    申请日：2018-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

    IPC: H01L23/535 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

    Abstract: According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

    Method and semiconductor apparatus for reducing power when transmitting data between devices in the semiconductor apparatus
    4.
    发明授权
    Method and semiconductor apparatus for reducing power when transmitting data between devices in the semiconductor apparatus 有权
    用于在半导体装置中的器件之间传输数据时降低功率的方法和半导体装置

    公开(公告)号：US09071239B2

    公开(公告)日：2015-06-30

    申请号：US13799686

    申请日：2013-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

    IPC: H03K17/00 ,  G11C7/10 ,  G11C7/02

    CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

    Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

    Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

    Standard cell architecture for gate tie-off
    5.
    发明授权
    Standard cell architecture for gate tie-off 有权

    公开(公告)号：US10784345B2

    公开(公告)日：2020-09-22

    申请号：US16781856

    申请日：2020-02-04

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

    IPC: H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

    Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

    Low-area low clock-power flip-flop
    8.
    发明授权
    Low-area low clock-power flip-flop 有权

    公开(公告)号：US09755618B1

    公开(公告)日：2017-09-05

    申请号：US15061055

    申请日：2016-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Seid Hadi Rasouli ,  Xiangdong Chen ,  Venugopal Boynapalli

    IPC: H03K3/12 ,  H03K3/012 ,  H03K3/356

    CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

    Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

    BUFFER TESTING FOR RECONFIGURABLE INSTRUCTION CELL ARRAYS
    9.
    发明申请
    BUFFER TESTING FOR RECONFIGURABLE INSTRUCTION CELL ARRAYS 有权
    用于可重构指令单元阵列的缓冲器测试

    公开(公告)号：US20150100842A1

    公开(公告)日：2015-04-09

    申请号：US14046084

    申请日：2013-10-04

    Applicant: QUALCOMM Incorporated

    Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

    Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

    Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

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