公开(公告)号：US20220068906A1

公开(公告)日：2022-03-03

申请号：US17010001

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Mohammed Yousuff Shariff

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：US11764186B2

公开(公告)日：2023-09-19

申请号：US17162621

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/58 ,  H03K17/687 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/58 ,  H01L24/16 ,  H03K17/6871 ,  H01L2224/16227

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US11430797B2

公开(公告)日：2022-08-30

申请号：US16917212

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Abinash Roy ,  Bharani Chava

IPC: H01L27/112 ,  H01L23/538 ,  H01L21/48

Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.

公开(公告)号：US11270991B1

公开(公告)日：2022-03-08

申请号：US17010001

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Mohammed Yousuff Shariff

IPC: H01L27/06 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：US11195793B2

公开(公告)日：2021-12-07

申请号：US16743350

申请日：2020-01-15

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.

公开(公告)号：US12057436B2

公开(公告)日：2024-08-06

申请号：US18365063

申请日：2023-08-03

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H03K17/687

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/58 ,  H01L24/16 ,  H03K17/6871 ,  H01L2224/16227

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The first power interconnect includes a first power plane. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The second power interconnect includes a second power plane. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US11830819B2

公开(公告)日：2023-11-28

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy ,  Stanley Seungchul Song ,  Jonghae Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20220165707A1

公开(公告)日：2022-05-26

申请号：US17100060

申请日：2020-11-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Bharani Chava

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking. To facilitate providing additional electrical routing paths for die-to-die interconnections between stacked IC dice in the IC package, a BS-BEOL metallization structure of a first die of the stacked dice of the IC package is stacked adjacent to a FS-BEOL metallization structure of a second die of the stacked IC dice. Electrical routing paths for die-to-die interconnections between the stacked IC dice are provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. It may be more feasible to form shorter electrical routing paths in the thinner BS-BEOL metallization structure than in a FS-BEM metallization structure for lower-resistance and/or lower-capacitance die-to-die interconnections for faster and/or compatible performance of semiconductor devices in the IC dice.

公开(公告)号：US11876085B2

公开(公告)日：2024-01-16

申请号：US17358838

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Abinash Roy ,  Lohith Kumar Vemula ,  Bharani Chava ,  Jonghae Kim

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64 ,  H01G4/232

CPC classification number: H01L25/16 ,  H01L21/4803 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/642 ,  H01G4/232

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.