公开(公告)号：US20180342515A1

公开(公告)日：2018-11-29

申请号：US16057036

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US20170117884A1

公开(公告)日：2017-04-27

申请号：US14921341

申请日：2015-10-23

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Animesh DATTA

IPC: H03K3/356 ,  G01R31/3185 ,  H03K3/037

CPC classification number: H03K3/356113 ,  H03K3/037 ,  H03K3/0375 ,  H03K3/35625

Abstract: A method and an apparatus for wireless communication are provided. The apparatus having a first latch having a first latch input and first latch output and a second latch having a second latch input, a second latch scan output, and a second latch data output. The second latch input is coupled to the first latch output. The apparatus further includes a selection component configured to select between a data input and a scan input based on a shift input. The selection component is coupled to the first latch input. The selection component includes a first NAND-gate, a second NAND-gate, and an OR-gate.

公开(公告)号：US20170221826A1

公开(公告)日：2017-08-03

申请号：US15493008

申请日：2017-04-20

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US20150054567A1

公开(公告)日：2015-02-26

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract translation: 互连电平上的第一互连将CMOS器件的PMOS漏极的第一子集连接在一起。 互连层上的第二互连将PMOS排水沟的第二子集连接在一起。 PMOS漏极的第二子集不同于PMOS漏极的第一子集。 第一互连和第二互连在互连级别上断开连接。 互连电平上的第三互连将CMOS器件的NMOS漏极的第一子集连接在一起。 互连电平上的第四互连将NMOS漏极的第二子集连接在一起。 NMOS漏极的第二子集与NMOS漏极的第一子集不同。 第三互连和第四互连在互连级别上断开。 第一，第二，第三和第四互连通过至少一个其它互连级连接在一起。

公开(公告)号：US20180211957A1

公开(公告)日：2018-07-26

申请号：US15927539

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael BRUNOLLI ,  Christine HAU-RIEGE ,  Mickael Sebtastien Alain MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

公开(公告)号：US20170353186A1

公开(公告)日：2017-12-07

申请号：US15171487

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Animesh DATTA ,  Bo PANG

IPC: H03K19/00 ,  H03K19/21 ,  H03K3/037

CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

Abstract: A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

公开(公告)号：US20170237434A1

公开(公告)日：2017-08-17

申请号：US15044988

申请日：2016-02-16

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Animesh DATTA ,  Venkatasubramanian NARAYANAN ,  Venugopal BOYNAPALLI

IPC: H03K19/003 ,  H03K3/037

CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

公开(公告)号：US20160344374A1

公开(公告)日：2016-11-24

申请号：US14720634

申请日：2015-05-22

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Steven James DILLEN ,  Animesh DATTA ,  Zhengyu DUAN ,  Satyanarayana SAHU ,  Praveen NARENDRANATH

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/012 ,  H03K3/037 ,  H03K5/131

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract translation: 脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。 锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。 脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。 延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。 延迟模块在延迟模块输出端提供功能上的I1IA，其中I1是I的函数，IA是IN0和B0的函数，其中I是延迟模块输入，B0是第一个输入位，IN0是第一个 净输入。

公开(公告)号：US20200168604A1

公开(公告)日：2020-05-28

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H01L23/528

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US20200152630A1

公开(公告)日：2020-05-14

申请号：US16744227

申请日：2020-01-16

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L23/535 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.