公开(公告)号：US20190013062A1

公开(公告)日：2019-01-10

申请号：US15644737

申请日：2017-07-07

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Gregory Michael WRIGHT ,  Shivam PRIYADARSHI ,  Garrett Michael DRAPALA ,  Harold Wade CAIN, III ,  Erik HEDBERG

IPC: G11C11/406 ,  G06F12/128 ,  G06F12/122 ,  G06F12/0871

Abstract: Systems and methods for selective refresh of a cache, such as a last-level cache implemented as an embedded DRAM (eDRAM). A refresh bit and a reuse bit are associated with each way of at least one set of the cache. A least recently used (LRU) stack tracks positions of the ways, with positions towards a most recently used position of a threshold comprising more recently used positions and positions towards a least recently used position of the threshold comprise less recently used positions. A line in a way is selectively refreshed if the position of the way is one of the more recently used positions and if the refresh bit associated with the way is set, or the position of the way is one of the less recently used positions and if the refresh bit and the reuse bit associated with the way are both set.

公开(公告)号：US20170083031A1

公开(公告)日：2017-03-23

申请号：US14860717

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Hoan Huu NGUYEN ,  Keith Alan BOWMAN ,  Yeshwant Nagaraj KOLLA ,  Burt Lee PRICE ,  Samantak GANGOPADHYAY

IPC: G05F1/56

CPC classification number: G05F1/56 ,  H03K19/0008

Abstract: Systems and methods relate to a low-dropout voltage (LDO) voltage regulator which receives a maximum supply voltage and provides a regulated voltage to a load, where the load may be a processing core of a multi-core processing system. A leakage current supply source includes a leakage current sensor to determine a leakage current demand of the load of the LDO voltage regulator and a leakage current supply circuit to supply the leakage current demand. In this manner, the leakage current supply source provides current assistance to the LDO voltage regulator, such that the LDO voltage regulator can supply only dynamic current. Thus, headroom voltage of the LDO voltage regulator, which is a difference between the maximum supply voltage and the regulated voltage, can be reduced. Reducing the headroom voltage allows greater number of dynamic voltage and frequency scaling states of the load.

公开(公告)号：US20230297335A1

公开(公告)日：2023-09-21

申请号：US17695824

申请日：2022-03-15

Applicant: QUALCOMM Incorporated

Inventor： Mustafa KESKIN ,  Francois Ibrahim ATALLAH

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50

Abstract: A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.

公开(公告)号：US20210225435A1

公开(公告)日：2021-07-22

申请号：US17223764

申请日：2021-04-06

Applicant: Qualcomm Incorporated

Inventor： Hoan Huu NGUYEN ,  Francois Ibrahim ATALLAH ,  Keith Alan BOWMAN ,  Daniel YINGLING ,  Jihoon JEONG ,  Yu PU

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US20200098422A1

公开(公告)日：2020-03-26

申请号：US16138174

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu NGUYEN ,  Francois Ibrahim ATALLAH ,  Keith Alan BOWMAN ,  Hari RAO

IPC: G11C11/419 ,  G11C11/4091 ,  G11C11/408 ,  G11C16/26 ,  G11C8/08 ,  G11C8/10 ,  G11C7/06

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

公开(公告)号：US20250103293A1

公开(公告)日：2025-03-27

申请号：US18472519

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Yatharth GUPTA

IPC: G06F7/544 ,  G06F5/01

Abstract: A method for multiplication and accumulation includes performing multiplications on a first set of bits and a second set of bits to generate first products, and performing multiplications on a third set of bits and a fourth set of bits to generate second products. The method also includes summing the first products to generate a first sum, changing a bit value of one of the second products, and summing the second products to generate a second sum. The method further includes averaging the first sum and the second sum to obtain an average of the first sum and the second sum, converting the average of the first sum and the second sum into a digital signal, and shifting and adding a one to the digital signal.

公开(公告)号：US20230078079A1

公开(公告)日：2023-03-16

申请号：US17472412

申请日：2021-09-10

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Hoan Huu NGUYEN ,  Colin Beaton VERRILLI ,  Natarajan VAIDHYANATHAN

IPC: G06N3/063 ,  G11C11/412

Abstract: A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.

公开(公告)号：US20230065725A1

公开(公告)日：2023-03-02

申请号：US17465550

申请日：2021-09-02

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Francois Ibrahim ATALLAH

IPC: G06N3/08 ,  G06F7/544 ,  G06N3/063 ,  G06N3/04

Abstract: Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved performance through depth parallelism. One example neural-network-processing circuit generally includes a plurality of groups of processing element (PE) circuits, wherein each group of PE circuits comprises a plurality of PE circuits configured to process in parallel an input at a plurality of depths.

公开(公告)号：US20160091918A1

公开(公告)日：2016-03-31

申请号：US14499152

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  David Joseph Winston HANSQUINE ,  Richard Duane TAX ,  Robert Simpson TAYLOR

IPC: G06F1/10 ,  H03K3/012

CPC classification number: G06F1/10 ,  G06F1/32 ,  G06F1/3237 ,  H03K3/012 ,  H03K19/0008 ,  H03K19/0019 ,  Y02D10/128

Abstract: Systems and methods are directed to a configurable last level driver coupled to a inductor-capacitor (LC) tank or resonant clock, for improving energy efficiency of the resonant clock. In a warm up stage, the last level clock driver can be enabled to store energy in the LC tank, and in a gating stage, the last level clock driver can be fully or partially disabled such that energy stored in the LC tank can be recirculated into a clock distribution network. In a refreshing stage, the last level clock driver can be enabled to replenish the energy lost by the LC tank in the recirculation of energy into the clock distribution network during the gating stage. Programmable counters can be used to control durations of the warm up, gating, and refreshing stages.

Abstract translation: 系统和方法涉及耦合到电感器 - 电容器（LC）箱或谐振时钟的可配置的最后级别驱动器，用于提高谐振时钟的能量效率。 在预热阶段，最后一级时钟驱动器可以使能在LC箱中存储能量，并且在选通阶段，最后一级时钟驱动器可以被完全或部分禁用，使得储存在LC箱中的能量可以再循环 进入时钟分配网络。 在更新阶段，可以启用最后一级时钟驱动器，以便在门控阶段期间将能量损失的能量补充到能量进入时钟分配网络中。 可编程计数器可用于控制预热，门控和刷新阶段的持续时间。