公开(公告)号：US20160239060A1

公开(公告)日：2016-08-18

申请号：US14622467

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Xufeng Chen ,  Robert Allan Lester ,  Manojkumar Pyla ,  Peixin Zhong

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3237 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/128 ,  Y02D10/171

Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

Abstract translation: 半导体器件的特征尺寸在每一代新一代继续下降。 较小的通道长度导致泄漏电流增加。 为了减少泄漏电流，在不活动期间，器件内部的一些电源域可能被断电（例如，电源崩溃）。 然而，当电力返回到折叠域时，其他电力域中的电路可能经历与重新配置到新供电域的通信信道相关联的显着处理开销。 在本公开中提供的是用于隔离功率域以促进柔性功率崩溃的示例性技术，同时更好地管理与重新建立数据连接相关联的处理开销。

公开(公告)号：US09142268B2

公开(公告)日：2015-09-22

申请号：US13719881

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett ,  Manojkumar Pyla ,  Robert A. Lester ,  Christopher E. Koob

IPC: G11C7/00 ,  G11C7/10 ,  G06F5/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。

公开(公告)号：US20130182515A1

公开(公告)日：2013-07-18

申请号：US13719881

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett ,  Manojkumar Pyla ,  Robert A. Lester ,  Christopher E. Koob

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。

公开(公告)号：US09785211B2

公开(公告)日：2017-10-10

申请号：US14622467

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Xufeng Chen ,  Robert Allan Lester ,  Manojkumar Pyla ,  Peixin Zhong

IPC: G06F1/26 ,  G06F1/32 ,  H03K19/00

CPC classification number: G06F1/26 ,  G06F1/3237 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/128 ,  Y02D10/171

Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

公开(公告)号：US09141544B2

公开(公告)日：2015-09-22

申请号：US13655593

申请日：2012-10-19

Applicant: QUALCOMM Incorporated

Inventor： Manojkumar Pyla ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0888 ,  G06F2212/601

Abstract: In a particular embodiment, a method of managing a cache memory includes, responsive to a cache size change command, changing a mode of operation of the cache memory to a write through/no allocate mode. The method also includes processing instructions associated with the cache memory while executing a cache clean operation when the mode of operation of the cache memory is the write through/no allocate mode. The method further includes after completion of the cache clean operation, changing a size of the cache memory and changing the mode of operation of the cache to a mode other than the write through/no allocate mode.

Abstract translation: 在特定实施例中，管理高速缓冲存储器的方法响应于高速缓存大小改变命令，将高速缓冲存储器的操作模式改变为写/无分配模式。 当高速缓冲存储器的操作模式是写/无分配模式时，该方法还包括处理与高速缓存存储器相关联的指令，同时执行高速缓存清理操作。 该方法还包括在完成高速缓存清理操作之后，改变高速缓冲存储器的大小并将高速缓存的操作模式改变为除了写/无分配模式以外的模式。

公开(公告)号：US20130346705A1

公开(公告)日：2013-12-26

申请号：US13655593

申请日：2012-10-19

Applicant: QUALCOMM INCORPORATED

Inventor： Manojkumar Pyla ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0888 ,  G06F2212/601

Abstract: In a particular embodiment, a method of managing a cache memory includes, responsive to a cache size change command, changing a mode of operation of the cache memory to a write through/no allocate mode. The method also includes processing instructions associated with the cache memory while executing a cache clean operation when the mode of operation of the cache memory is the write through/no allocate mode. The method further includes after completion of the cache clean operation, changing a size of the cache memory and changing the mode of operation of the cache to a mode other than the write through/no allocate mode.

Abstract translation: 在特定实施例中，管理高速缓冲存储器的方法响应于高速缓存大小改变命令，将高速缓冲存储器的操作模式改变为写/无分配模式。 当高速缓冲存储器的操作模式是写/无分配模式时，该方法还包括处理与高速缓存存储器相关联的指令，同时执行高速缓存清理操作。 该方法还包括在完成高速缓存清理操作之后，改变高速缓冲存储器的大小并将高速缓存的操作模式改变为除了写/无分配模式以外的模式。