公开(公告)号：US20170068772A1

公开(公告)日：2017-03-09

申请号：US15258923

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Kelageri NAGARAJ ,  Paras GUPTA ,  Thomas YU ,  Venkatesh NAYAK ,  Anil Kumar KODURU ,  Bhanuprakash GANGULA VENKATARAMA REDDY

IPC: G06F17/50 ,  H03K5/13 ,  H03K19/00

CPC classification number: G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H03K5/13 ,  H03K19/0008 ,  H03K2005/00019

Abstract: A method of and an apparatus for optimizing timing delay and power leakage in a circuit. The apparatus determines at least one path of a plurality of paths in a network of logic elements, the at least one path including a plurality of cells, each of the cells being configured to perform a logical operation. In addition, the apparatus identifies a first cell of the plurality of cells based on a first cost factor associated with replacing the first cell with a first replacement cell that performs the same logical operation, the first cost factor being a function of a power leakage difference and a timing delay difference associated with the first cell and the first replacement cell. Furthermore, the apparatus replaces the first cell with the first replacement cell in the at least one path.

Abstract translation: 一种用于优化电路中的定时延迟和功率泄漏的方法和装置。 所述装置确定逻辑元件的网络中的多个路径的至少一个路径，所述至少一个路径包括多个小区，每个小区被配置为执行逻辑运算。 此外，该装置基于与执行相同逻辑运算的第一替换单元替换第一单元相关联的第一成本因素来识别多个单元中的第一单元，第一成本因子是功率泄漏差的函数 以及与第一小区和第一替换小区相关联的定时延迟差异。 此外，装置用至少一个路径中的第一替换单元替换第一单元。

公开(公告)号：US20230221789A1

公开(公告)日：2023-07-13

申请号：US18000319

申请日：2021-07-28

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Smeeta HEGGOND ,  Jitu Khushalbhai MISTRY ,  Paras GUPTA ,  Keyurkumar Karsanbhai KANSAGRA ,  Kamesh MEDISETTI ,  Ramaprasath VILANGUDIPITCHAI ,  Arshath SHEEPARAMATTI

IPC: G06F1/3296 ,  G06F1/26 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/263 ,  G06F1/3275

Abstract: A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

公开(公告)号：US20150262936A1

公开(公告)日：2015-09-17

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta BANSAL ,  Uday DODDANNAGARI ,  Paras GUPTA ,  Ramaprasath VILANGUDIPITCHAI ,  Parissa NAJDESAMII ,  Dorav KUMAR ,  Nitin PARTANI

IPC: H01L23/538 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。