公开(公告)号：US20240231982A9

公开(公告)日：2024-07-11

申请号：US18489809

申请日：2023-10-18

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Vasant Kumar EASWARAN ,  Rahul GULATI

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/079 ,  G06F11/0793

Abstract: Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.

公开(公告)号：US20180331692A1

公开(公告)日：2018-11-15

申请号：US15594322

申请日：2017-05-12

Applicant: QUALCOMM Incorporated

Inventor： Rahul GULATI ,  Palkesh JAIN ,  Pranjal BHUYAN ,  Mohammad Reza KAKOEE

IPC: H03M13/01 ,  H03M13/00

CPC classification number: H03M13/015 ,  G06F11/2215 ,  H03M13/6566

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

公开(公告)号：US20190065785A1

公开(公告)日：2019-02-28

申请号：US15685795

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： David Barr ,  Dafna SHAOOL ,  Rahul GULATI ,  Pranjal BHUYAN

IPC: G06F21/70 ,  G06F21/62 ,  G06F21/50

CPC classification number: G06F21/70 ,  B60W50/00 ,  F02N11/0807 ,  G06F9/5011 ,  G06F21/00 ,  G06F21/44 ,  G06F21/50 ,  G06F21/6218 ,  G06F2221/2129

Abstract: A computing device includes a hardware resource, a component to send a transaction signal including a target address of the hardware resource, a security data associated with an initiator of the transaction signal, and a safety data associated with the initiator, and an access control unit coupled to the component and the hardware resource, the access control unit to receive the transaction signal, determine whether security access is granted based on the transaction signal, determine whether safety access is granted based on the transaction signal, and allow access to the hardware resource based on both the security access and the safety access being granted.

公开(公告)号：US20180203778A1

公开(公告)日：2018-07-19

申请号：US15410271

申请日：2017-01-19

Applicant: QUALCOMM Incorporated

Inventor： Kapil BANSAL ,  Kailash DIGARI ,  Rahul GULATI

IPC: G06F11/273 ,  G06F11/22

CPC classification number: G06F11/273 ,  G06F11/1645 ,  G06F11/2215 ,  G06F11/2242 ,  G06F2201/805

Abstract: Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.

公开(公告)号：US20240296702A1

公开(公告)日：2024-09-05

申请号：US18176902

申请日：2023-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： Amit ANEJA ,  Rahul GULATI ,  Sriram HARIHARAN

IPC: G07C5/08 ,  G01R31/00

CPC classification number: G07C5/0808 ,  G01R31/007 ,  B60R16/023 ,  B60W50/0225

Abstract: Fail-safe and Fail-operational behavior can be achieved by providing two fully-redundant execution channels comprising at least first and second chiplet dies on a single SoC that are in communication with one another via a D2D interface. At least first and second instances of a first automotive safety integrity level (ASIL) domain circuit disposed on the at least first and second chiplet dies, respectively, perform at least a first ASIL domain process on one or more automotive sensor output signals to produce first and second output signals, respectively. A fault monitoring system monitors at least the first chiplet die for faults and assigns a first value to a selector signal if it detects a fault in the first chiplet die. A selector circuit outputs the second output signal from the system if the selector signal has the first value.

公开(公告)号：US20210294398A1

公开(公告)日：2021-09-23

申请号：US16826729

申请日：2020-03-23

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI

IPC: G06F1/20 ,  G01R31/317 ,  G06F1/3203

Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

公开(公告)号：US20200072885A1

公开(公告)日：2020-03-05

申请号：US16118280

申请日：2018-08-30

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI ,  Edward Jacob MEISAROSH

IPC: G01R29/027 ,  H03K3/037 ,  G06F1/10

Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

公开(公告)号：US20250110174A1

公开(公告)日：2025-04-03

申请号：US18479598

申请日：2023-10-02

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI ,  Niraj Shantilal PALIWAL ,  Nikhil Rajendra PATIL ,  Vipul Deepak AHUJA

IPC: G01R31/28 ,  H01L23/367

Abstract: Methods and apparatuses directed to detecting the degradation of electronic components based on thermal testing. In some examples, a device includes heat detection elements, a temperature controller, a memory, and a processor. The temperature controller can receive a signal from each of the heat detection elements and determine a corresponding operating temperature. The processor can receive the operating temperatures from the temperature controller, and can read from the memory a threshold temperature corresponding to each of the heat detection elements. Further, the processor can compare the operating temperatures to their corresponding threshold temperatures and, based on the comparison, generate thermal error data characterizing detected thermal discrepancies. The processor can transmit the thermal error data to cause further operations, such as the disabling of a safety feature, or the display of a warning message, for example.

公开(公告)号：US20240323344A1

公开(公告)日：2024-09-26

申请号：US18188863

申请日：2023-03-23

Applicant: QUALCOMM INCORPORATED

Inventor： Abhijeet DEY ,  Rahul GULATI ,  Joby ABRAHAM ,  Vijayamanohar NAGARAJAN ,  Aakil Mahendra BAPNA

IPC: H04N17/00

CPC classification number: H04N17/002

Abstract: An image processing system includes an image sensor configured to generate a video frame, the video frame having a data portion and a test portion, an inline front end (IFE) having at least one processing module, a first memory, a functional software register, and a test software register, the IFE configured to receive the video frame, process the video frame and store the processed video frame to a second memory, a test pattern generator configured to generate test data that is provided to the IFE during the test portion of the video frame, a multiple input signature register (MISR) test function configured to compute a MISR signature from the test data, and a comparison function configured to compare a verified version of the test data to the computed MISR signature in the IFE to determine whether a system interrupt should be generated.

公开(公告)号：US20240134730A1

公开(公告)日：2024-04-25

申请号：US18489809

申请日：2023-10-17

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Vasant Kumar EASWARAN ,  Rahul GULATI

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/079 ,  G06F11/0793

Abstract: Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.