公开(公告)号：US20180331692A1

公开(公告)日：2018-11-15

申请号：US15594322

申请日：2017-05-12

Applicant: QUALCOMM Incorporated

Inventor： Rahul GULATI ,  Palkesh JAIN ,  Pranjal BHUYAN ,  Mohammad Reza KAKOEE

IPC: H03M13/01 ,  H03M13/00

CPC classification number: H03M13/015 ,  G06F11/2215 ,  H03M13/6566

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

公开(公告)号：US20250110174A1

公开(公告)日：2025-04-03

申请号：US18479598

申请日：2023-10-02

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI ,  Niraj Shantilal PALIWAL ,  Nikhil Rajendra PATIL ,  Vipul Deepak AHUJA

IPC: G01R31/28 ,  H01L23/367

Abstract: Methods and apparatuses directed to detecting the degradation of electronic components based on thermal testing. In some examples, a device includes heat detection elements, a temperature controller, a memory, and a processor. The temperature controller can receive a signal from each of the heat detection elements and determine a corresponding operating temperature. The processor can receive the operating temperatures from the temperature controller, and can read from the memory a threshold temperature corresponding to each of the heat detection elements. Further, the processor can compare the operating temperatures to their corresponding threshold temperatures and, based on the comparison, generate thermal error data characterizing detected thermal discrepancies. The processor can transmit the thermal error data to cause further operations, such as the disabling of a safety feature, or the display of a warning message, for example.

公开(公告)号：US20170300080A1

公开(公告)日：2017-10-19

申请号：US15133068

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Virendra BANSAL ,  Manoj MEHROTRA ,  Keith Alan BOWMAN

IPC: G06F1/04 ,  G06F1/26 ,  H03K3/03 ,  H03L7/06

CPC classification number: G06F1/04 ,  G06F1/08 ,  G06F1/26 ,  G06F1/305 ,  H03K3/0315 ,  H03L7/06

Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

公开(公告)号：US20210294398A1

公开(公告)日：2021-09-23

申请号：US16826729

申请日：2020-03-23

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI

IPC: G06F1/20 ,  G01R31/317 ,  G06F1/3203

Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

公开(公告)号：US20200072885A1

公开(公告)日：2020-03-05

申请号：US16118280

申请日：2018-08-30

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI ,  Edward Jacob MEISAROSH

IPC: G01R29/027 ,  H03K3/037 ,  G06F1/10

Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

公开(公告)号：US20170115710A1

公开(公告)日：2017-04-27

申请号：US14920218

申请日：2015-10-22

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Manoj MEHROTRA

IPC: G06F1/26 ,  G06F1/28

CPC classification number: G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  H02J7/0063 ,  H02J2007/0067

Abstract: Apparatuses and methods to adjust a source voltage based on stored information are provided. The apparatus includes a circuit configured to receive power from a power source through a power distribution network, a storage medium storing data specifying one or more electrical characteristics of the circuit, and a control circuit configured to adjust a source voltage at the power source based on the data stored in the storage medium. The method includes receiving power by a circuit from a power source through a power distribution network, reading data specifying one or more electrical characteristics of the circuit from a storage medium, and adjusting a source voltage at the power source based on the data stored in the storage medium.

公开(公告)号：US20210234376A1

公开(公告)日：2021-07-29

申请号：US16774023

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI

IPC: H02J4/00 ,  G06F1/3203 ,  H01L23/525 ,  H02J9/00 ,  H01L27/08 ,  G06F1/18

Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

公开(公告)号：US20200019477A1

公开(公告)日：2020-01-16

申请号：US16031813

申请日：2018-07-10

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI

IPC: G06F11/16 ,  G01R31/317 ,  G06F1/10 ,  G06F11/18

Abstract: In one embodiment, a system has an integrated circuit (IC) device, the IC device includes a first processing unit having a first functional block that has a diversifiable sub-circuit and a result output, a second processing unit having a second functional block substantially identical to the first functional block that includes a corresponding diversifiable sub-circuit and a corresponding result output. The IC device includes a comparator adapted to compare the result output of the first functional block to the result output of the second functional block. The diversifiable sub-circuit of the first functional block operates using a first set of operating parameters. The diversifiable sub-circuit of the second functional block operates using a second set of operating parameters different from the first set of operating parameters.

公开(公告)号：US20170257079A1

公开(公告)日：2017-09-07

申请号：US15058001

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Manoj MEHROTRA ,  Yuancheng Chris PAN ,  Shih-Hsin Jason HU

IPC: H03K3/011 ,  G06F1/32

CPC classification number: H03K3/011 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/172

Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.