公开(公告)号：US11347667B2

公开(公告)日：2022-05-31

申请号：US16243698

申请日：2019-01-09

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Sharon Graif ,  Shaul Yohai Yifrach

IPC: G06F11/07 ,  G06F11/30 ,  G06F13/20 ,  G06F13/42 ,  G06F13/362

Abstract: The disclosure includes systems and methods for bus control. A method comprises receiving a data exchange request, wherein the data exchange request includes a data exchange tag that identifies a data exchange, splitting the data exchange into a plurality of fractional data transactions, providing one or more bus commands to a system bus, receiving, at the bus controller, one or more acceptance notifications indicating that the one or more of the plurality have been accepted by the system bus, assigning transaction identifiers (TIDs) corresponding to the one or more of the plurality of fractional data transactions, receiving one or more completion notifications indicating that the one or more of the plurality have been completed, determining that each of the plurality of fractional data transactions associated with the data exchange tag have been completed, and notifying the processor that the requested data exchange has been completed.

公开(公告)号：US11327922B2

公开(公告)日：2022-05-10

申请号：US16997505

申请日：2020-08-19

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Sai Ganapathy Srinivasan ,  Navdeep Mer ,  Sriharsha Chakka

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/08

Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

公开(公告)号：US20210382677A1

公开(公告)日：2021-12-09

申请号：US16894096

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Jason Gonzalez

IPC: G06F3/16 ,  G06F13/362 ,  G06F13/42 ,  G06F13/40

Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

公开(公告)号：US20190354502A1

公开(公告)日：2019-11-21

申请号：US16409030

申请日：2019-05-10

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Lior Amarilio ,  Sharon Graif

IPC: G06F13/40 ,  G06F13/42 ,  G06F11/10

Abstract: Lightweight Universal Serial Bus (USB) compound device implementation is disclosed. In particular, a compound device is provided that includes a parsing circuit that parses addresses and endpoint values for comparison to a look-up table and translation thereof for provision of updated addresses and endpoint values to a USB device controller. The USB device controller then uses the updated endpoint values to route information to a correct destination. In this manner, the benefits of a USB compound device are provided without the area and power penalty that normally accompanies a USB compound device.

公开(公告)号：US09524264B2

公开(公告)日：2016-12-20

申请号：US14316026

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  David Asher Friedman ,  Ben Levin ,  Sharon Graif

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4226 ,  G06F13/364 ,  G06F13/4291

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract translation: 公开了在共享总线系统中使用异步主设备参考时钟生成组合总线时钟信号，以及相关方法，设备和计算机可读介质。 一方面，一种用于产生组合总线时钟信号的方法包括：通过通信耦合到共享总线的共享时钟线的多个主设备的每个主设备检测起始事件。 每个主设备在主设备的参考时钟信号的相应多个转换处对共享时钟线的多个共享时钟线值进行采样。 每个主设备确定多个共享时钟线值是否相同。 如果共享时钟线路值相同，则在主设备的参考时钟信号的下一个转换处，每个主设备将共享时钟线驱动值与多个共享时钟线路值相反地驱动到共享时钟线路。

公开(公告)号：US11704086B2

公开(公告)日：2023-07-18

申请号：US16894096

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Jason Gonzalez

IPC: G06F3/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/362

CPC classification number: G06F3/162 ,  G06F13/3625 ,  G06F13/4072 ,  G06F13/4282

Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

公开(公告)号：US11520729B2

公开(公告)日：2022-12-06

申请号：US17307842

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Sharon Graif ,  Lior Amarilio ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

公开(公告)号：US20200293081A1

公开(公告)日：2020-09-17

申请号：US16353426

申请日：2019-03-14

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Ghanashyam Prabhu ,  Sharon Graif

IPC: G06F1/08 ,  G06F13/24 ,  H04B1/20 ,  H04L7/00 ,  G06F11/07

Abstract: Systems and methods for power conservation on an audio bus through clock manipulation allow a clock signal on an audio bus such as a SOUNDWIRE audio bus to be stopped when there are no pending commands from a master device. The clock signal may resume when a new command from the master device is generated or the master device receives an interrupt from a slave device.

公开(公告)号：US10725949B2

公开(公告)日：2020-07-28

申请号：US16115388

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/32 ,  G06F1/10 ,  G06F1/3296 ,  G06F1/3293 ,  G06F1/3287

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

公开(公告)号：US10684981B2

公开(公告)日：2020-06-16

申请号：US16381189

申请日：2019-04-11

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Sharon Graif ,  Richard Dominic Wietfeldt

IPC: G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.