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公开(公告)号：US12079897B2
公开(公告)日：2024-09-03
申请号：US17935031
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar Bhiravabhatla , Andrew Evan Gruber , Rahul Sunil Kukreja , Vishwanath Shashikant Nikam , Tao Wang , Jian Liang
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/405
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20210383545A1
公开(公告)日：2021-12-09
申请号：US16892096
申请日：2020-06-03
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Srihari Babu Alla , Kalyan Kumar Bhiravabhatla , Jonnala Gadda Nagendra Kumar , William Licea-Kane , Fredrick Alan Hickman
Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.
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公开(公告)号：US20200273142A1
公开(公告)日：2020-08-27
申请号：US16282003
申请日：2019-02-21
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Tao Wang , Shangmei Yu , Jing Gao , Jian Liang , Andrew Evan Gruber , Chun Yu
Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.
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公开(公告)号：US10445902B2
公开(公告)日：2019-10-15
申请号：US15377801
申请日：2016-12-13
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Serag GadelRab , Zhenbiao Ma , Meghal Varia , Tao Wang , Tom Longo , Mark Sternberg , Paul Chow
Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.
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公开(公告)号：US20180165789A1
公开(公告)日：2018-06-14
申请号：US15377801
申请日：2016-12-13
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Serag GadelRab , Zhenbiao Ma , Meghal Varia , Tao Wang , Tom Longo , Mark Sternberg , Paul Chow
CPC classification number: G06T11/001 , G06T1/20 , G06T11/40 , G09G5/363 , G09G5/395 , G09G2340/02 , G09G2340/16 , G09G2350/00 , G09G2360/121 , G09G2360/122 , G09G2360/18
Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.
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Patent Agency Ranking
公开(公告)号：US09824458B2
公开(公告)日：2017-11-21
申请号：US14862532
申请日：2015-09-23
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Yang Xia , Xuefeng Tang , Jian Liang , Tao Wang , Andrew Evan Gruber , Eric Demers
CPC classification number: G06T7/20 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/28
Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.
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公开(公告)号：US20160232645A1
公开(公告)日：2016-08-11
申请号：US14618463
申请日：2015-02-10
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang
CPC classification number: G06T1/60 , G06F9/50 , G06T1/20 , G06T15/005 , G06T15/04 , G06T15/80 , G06T2200/28 , G06T2210/08
Abstract: This disclosure presents techniques and structures for graphics processing. In one example, a method of graphics processing may include rendering, with a graphics processing unit (GPU), one or more portions of a frame using one or more graphics operations, and writing, with the GPU, color data directly to a color buffer in a system memory in accordance with the one or more graphics operations. The method may further include writing, with the GPU, depth data to a depth buffer in a graphics memory in accordance with the one or more graphics operations, and resolving, with the GPU, the depth buffer in the graphics memory to the system memory when the rendering of the one or more portions of the frame is complete.
Abstract translation: 本公开提供用于图形处理的技术和结构。 在一个示例中，图形处理的方法可以包括使用图形处理单元（GPU），使用一个或多个图形操作来渲染帧的一个或多个部分，并且将GPU与彩色数据直接写入颜色缓冲器 在根据一个或多个图形操作的系统存储器中。 该方法还可以包括根据一个或多个图形操作将GPU深度数据写入图形存储器中的深度缓冲器，并且在GPU中将图形存储器中的深度缓冲器解析为系统存储器，当 帧的一个或多个部分的呈现完成。
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8.发明授权Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations 有权用于执行图形处理单元的存储器传送操作的多模式存储器存取技术公开(公告)号：US09245496B2
公开(公告)日：2016-01-26
申请号：US13725393
申请日：2012-12-21
Applicant: QUALCOMM Incorporated
Inventor： Andrew E. Gruber , Tao Wang , Shambhoo Khandelwal
CPC classification number: G09G5/363 , G06F12/0607 , G06F12/0875 , G06F2212/1021 , G06F2212/455 , G06F2212/601 , G09G5/393 , G09G5/395
Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.
Abstract translation: 本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。 在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式使用GPU执行存储器传送操作。 可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。 本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。
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9.发明申请MULTI-MODE MEMORY ACCESS TECHNIQUES FOR PERFORMING GRAPHICS PROCESSING UNIT-BASED MEMORY TRANSFER OPERATIONS 有权用于执行图形处理的多模式存储器访问技术基于单元的存储器传输操作公开(公告)号：US20140176586A1
公开(公告)日：2014-06-26
申请号：US13725393
申请日：2012-12-21
Applicant: QUALCOMM INCORPORATED
Inventor： Andrew E. Gruber , Tao Wang , Shambhoo Khandelwal
IPC: G09G5/36
CPC classification number: G09G5/363 , G06F12/0607 , G06F12/0875 , G06F2212/1021 , G06F2212/455 , G06F2212/601 , G09G5/393 , G09G5/395
Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.
Abstract translation: 本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。 在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式，使用GPU执行存储器传送操作。 可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。 本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。
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公开(公告)号：US11373267B2
公开(公告)日：2022-06-28
申请号：US16673564
申请日：2019-11-04
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Shambhoo Khandelwal , Andrew Evan Gruber , Shangmei Yu , Jing Gao , Junmei Shao , Thomas Edwin Frisinger , Rick Hammerstone
Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
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