公开(公告)号：US09465749B2

公开(公告)日：2016-10-11

申请号：US13969559

申请日：2013-08-17

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/02 ,  G06F12/10 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract translation: 具有预取地址发生器的系统，其耦合到包括翻译高速缓存的系统转换后备缓冲器。 发送预取请求以进行页面地址转换，以便将来预测未来的正常请求。 预取请求被过滤，只能发布用于不太可能在翻译缓存中的地址转换。 待处理的预取请求仅限于可配置或可编程的数字。 这种系统是从硬件描述语言表示模拟的。

公开(公告)号：US09563560B2

公开(公告)日：2017-02-07

申请号：US13938675

申请日：2013-07-10

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0833

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Abstract translation: 一个一致性控制器（例如在片上系统中使用的控制器）能够向相干缓存发出不同类型的监听。 一致性控制器根据引起窥探或系统状态或两者的请求的类型选择窥探的类型。 通过这样做，一致的高速缓存在它们具有足够的吞吐量时提供数据，并且当它们没有足够的吞吐量时不需要提供数据。

公开(公告)号：US09170949B2

公开(公告)日：2015-10-27

申请号：US14040643

申请日：2013-09-28

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0833

Abstract: A simplified coherency controller supports multiple exclusively active fully coherent agent interfaces and any number of active I/O (partially) coherent agent interfaces. A state controller determines which fully coherent agent is active. Multiple fully coherent agents can be simultaneously active during a short period of a transition of processing from one to another processor. Multiple fully coherent agents can be simultaneously active, though without a mutually consistent view of memory, which is practical in cases such as when running multiple operating systems on different processors.

Abstract translation: 简化的一致性控制器支持多个专有活动的完全相干代理接口和任意数量的活动I / O（部分）协调代理接口。 状态控制器确定哪个完全相干代理是活动的。 在从一个处理器到另一个处理器的处理过渡的短暂时间段期间，多个完全相干代理可以同时处于活动状态。 尽管没有相互一致的存储器视图，但是多个完全一致的代理可以同时处于活动状态，这在诸如在不同处理器上运行多个操作系统的情况下是实用的。

公开(公告)号：US08930638B2

公开(公告)日：2015-01-06

申请号：US13686604

申请日：2012-11-27

Applicant: QUALCOMM Technologies, Inc.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而无需修改或副作用。

公开(公告)号：US09396130B2

公开(公告)日：2016-07-19

申请号：US13969451

申请日：2013-08-16

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Philippe Boucard ,  Jean-Jacques LeCler ,  Laurent Moll

IPC: G06F12/08 ,  G06F12/10 ,  G06F17/50 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract translation: 系统TLB集成在互连中，使用并共享传输网络连接到共享步进端口。 事务能够通过第二发起方侧互连传递STLB分配信息，其中互连可以级联，以便允许发起者控制第一互连中的共享STLB。 在第一个互连中，多个STLB共享中间级转换缓存，当在两个STLB的请求之间存在局部性时，可提高性能。

公开(公告)号：US09141556B2

公开(公告)日：2015-09-22

申请号：US13969425

申请日：2013-08-16

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques LeCler ,  Philippe Boucard

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/08 ,  G06F17/50 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract translation: 系统TLB接受来自发起者的翻译预取请求。 Misses会向Walker端口生成外部翻译请求。 诸如ID，地址和类的请求的属性以及TLB的状态会影响多级翻译表中的翻译分配策略。 翻译表用SRAM实现，并组织成组。

公开(公告)号：US20140149687A1

公开(公告)日：2014-05-29

申请号：US13686604

申请日：2012-11-27

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而不进行修改或副作用。