公开(公告)号：US20160064538A1

公开(公告)日：2016-03-03

申请号：US14837053

申请日：2015-08-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/15 ,  H01L29/66 ,  H01L29/207 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有在衬底上形成的含有ap型杂质，沟道层和阻挡层的电位固定层，以及布置在穿过势垒层的沟槽中的栅极，并且通过沟道层的某一点通过 门绝缘膜。 源极和漏极形成在栅电极的相对侧上。 含p型杂质的电位固定层在栅电极和漏电极之间具有含有诸如氢之类的钝化元件的失活区域。 因此，在提高源电极侧的电位固定层的p型杂质（受体）浓度的同时，在漏电极侧使电位固定层的p型杂质失活。 这可以提高漏极侧击穿电压，同时通过p型杂质提供电荷的去除效果。

公开(公告)号：US20180061983A1

公开(公告)日：2018-03-01

申请号：US15789191

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170294538A1

公开(公告)日：2017-10-12

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170047437A1

公开(公告)日：2017-02-16

申请号：US15216817

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L21/02 ,  H01L21/324 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/2258 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/808

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has an impurity-containing potential fixed layer, and a gate electrode. A drain electrode and a source electrode are formed on the opposite sides of the gate electrode. An interlayer insulation film is formed between the gate electrode and the drain electrode, and between the gate electrode and the source electrode. The concentration of the inactivating element in the portion of the potential fixed layer under the drain electrode is higher than the concentration of the inactivating element in the portion of the potential fixed layer under the source electrode. The film thickness of the portion of the interlayer insulation film between the gate electrode and the drain electrode is different from the film thickness of the portion of the interlayer insulation film between the gate electrode and the source electrode.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有含杂质的电位固定层和栅电极。 漏电极和源电极形成在栅电极的相对侧上。 在栅电极和漏电极之间以及栅电极和源电极之间形成层间绝缘膜。 在漏电极下方的电位固定层部分中的灭活元件的浓度高于源电极下的电位固定层部分中的钝化元件的浓度。 栅电极和漏电极之间的层间绝缘膜的部分的膜厚度与栅电极和源电极之间的层间绝缘膜的部分的膜厚不同。