公开(公告)号：US20180076312A1

公开(公告)日：2018-03-15

申请号：US15818638

申请日：2017-11-20

Applicant: Renesas Electronics Corporation

Inventor： Shinichi MIYAKE ,  Tatsuo NAKAYAMA

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L23/29 ,  H01L29/43 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.

公开(公告)号：US20170250274A1

公开(公告)日：2017-08-31

申请号：US15386746

申请日：2016-12-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/02694 ,  H01L21/2258 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/266 ,  H01L29/0688 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7783

Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

公开(公告)号：US20160079409A1

公开(公告)日：2016-03-17

申请号：US14947172

申请日：2015-11-20

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0≦z≦1). The channel layer includes a composition of AlxGa1-xN (0≦x≦1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.

Abstract translation: 一种包括场效应晶体管的半导体器件，包括衬底，设置在衬底上的下阻挡层，设置在下阻挡层上的沟道层，设置在沟道层上的电子供给层，设置在沟道层上的源电极和漏电极 电子层和设置在源电极和漏电极之间的栅电极。 下阻挡层包括In1-zAlzN（0＆nlE; z＆nlE; 1）的组合物。 沟道层包括Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）的组成。 在源电极和漏电极之间的区域设置有凹部，其中，凹部穿过电子供给层到达暴露沟道层的深度，并且栅电极设置在覆盖底面的栅极绝缘膜上 和凹部的内壁表面。

公开(公告)号：US20150221757A1

公开(公告)日：2015-08-06

申请号：US14604796

申请日：2015-01-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L23/522 ,  H01L29/15

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

Abstract translation: 提高了半导体器件的特性。 半导体器件被配置为提供穿透阻挡层的沟槽，并且到达n +层，n型层，p型层，沟道层和势垒层中的沟道层的中间部分，其中 形成在基板上方，通过栅极绝缘膜布置在沟槽内的栅电极，以及形成在栅电极两侧的势垒层上方的源电极和漏电极。 n型层和漏电极通过到达n +层的连接部分彼此电耦合。 p型层和源电极通过到达p型层的连接部分彼此电耦合。 在源电极和漏电极之间设置包括p型层和n型层的二极管，从而防止由雪崩击穿引起的元件断裂。

公开(公告)号：US20180061983A1

公开(公告)日：2018-03-01

申请号：US15789191

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170294538A1

公开(公告)日：2017-10-12

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170186880A1

公开(公告)日：2017-06-29

申请号：US15363386

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/30 ,  H01L29/20

CPC classification number: H01L29/78681 ,  H01L21/3006 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/66522 ,  H01L29/78

Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

公开(公告)号：US20160293709A1

公开(公告)日：2016-10-06

申请号：US15076753

申请日：2016-03-22

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO

IPC: H01L29/201 ,  H01L21/768 ,  H01L29/423 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76898 ,  H01L29/1087 ,  H01L29/207 ,  H01L29/34 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.

Abstract translation: 提高了半导体器件的特性。 半导体器件包括电压钳位层，沟道基极层，沟道层和衬底上的阻挡层。 沟槽通过阻挡层延伸到沟道层的一定深度。 栅电极设置在沟槽内的栅极绝缘膜上。 源电极和漏极设置在栅电极的两个侧面上。 延伸到电压钳位层的通孔内的耦合将电压钳位层电耦合到源电极。 在通孔下面设置含有比p型杂质更高的受体水平的杂质的杂质区域。 电压钳位层减小阈值电压和导通电阻等特性的变化。 由于杂质区域中的杂质，接触电阻由于跳跃导通而降低。

公开(公告)号：US20180219089A1

公开(公告)日：2018-08-02

申请号：US15841676

申请日：2017-12-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/66431 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789

Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

公开(公告)号：US20180026099A1

公开(公告)日：2018-01-25

申请号：US15604848

申请日：2017-05-25

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAMA ,  Atsushi TSUBOI ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/1087 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.