公开(公告)号：US20250015138A1

公开(公告)日：2025-01-09

申请号：US18892925

申请日：2024-09-23

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20160079409A1

公开(公告)日：2016-03-17

申请号：US14947172

申请日：2015-11-20

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0≦z≦1). The channel layer includes a composition of AlxGa1-xN (0≦x≦1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.

Abstract translation: 一种包括场效应晶体管的半导体器件，包括衬底，设置在衬底上的下阻挡层，设置在下阻挡层上的沟道层，设置在沟道层上的电子供给层，设置在沟道层上的源电极和漏电极 电子层和设置在源电极和漏电极之间的栅电极。 下阻挡层包括In1-zAlzN（0＆nlE; z＆nlE; 1）的组合物。 沟道层包括Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）的组成。 在源电极和漏电极之间的区域设置有凹部，其中，凹部穿过电子供给层到达暴露沟道层的深度，并且栅电极设置在覆盖底面的栅极绝缘膜上 和凹部的内壁表面。

公开(公告)号：US20240290881A1

公开(公告)日：2024-08-29

申请号：US18638883

申请日：2024-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0274 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/4916

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210217888A1

公开(公告)日：2021-07-15

申请号：US17216136

申请日：2021-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20190074174A1

公开(公告)日：2019-03-07

申请号：US16052929

申请日：2018-08-02

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Takashi IDE

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02356 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/432 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7783

Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.

公开(公告)号：US20190051740A1

公开(公告)日：2019-02-14

申请号：US16028128

申请日：2018-07-05

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L29/778 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L23/5329 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: In a manufacturing method of a semiconductor device according to the present invention, a buffer layer including a first nitride semiconductor layer, a channel layer including a second nitride semiconductor layer, and a barrier layer including a third nitride semiconductor layer are sequentially laminated, and a fourth nitride semiconductor layer is further laminated thereover. Then, a laminate of a gate insulating film and a gate electrode is formed over a first region of the fourth nitride semiconductor layer, and a silicon nitride film is formed over the fourth nitride semiconductor layer and the laminate. By bringing the fourth nitride semiconductor layers on both sides of the gate electrode into contact with the silicon nitride film in this way, the function of suppressing 2DEG can be lowered, and the 2DEG that has been eliminated after the formation of the fourth nitride semiconductor layer can be restored. The lowering in the function of suppressing 2DEG is maintained even after the silicon nitride film is removed.

公开(公告)号：US20170358652A1

公开(公告)日：2017-12-14

申请号：US15670982

申请日：2017-08-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/42368 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/66462 ,  H01L29/7786

Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.

公开(公告)号：US20170288046A1

公开(公告)日：2017-10-05

申请号：US15463320

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI ,  Tatsuo NAKAYAMA

IPC: H01L29/778 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/30612 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7786

Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (θ1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

公开(公告)号：US20160005846A1

公开(公告)日：2016-01-07

申请号：US14829216

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alxα1-xN layer (α includes Ga or In, and 0

Abstract translation: 半导体器件包括第一半导体层，形成在第一半导体层上的第二半导体层，与第二半导体层接触的栅极绝缘膜，以及经由栅极绝缘膜与第二半导体层相对的栅电极。 第一半导体层包括Al xα1-x N层（α包括Ga或In，并且0