公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210028306A1

公开(公告)日：2021-01-28

申请号：US17060486

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US20180097070A1

公开(公告)日：2018-04-05

申请号：US15679600

申请日：2017-08-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO

IPC: H01L29/20 ,  H01L23/66 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/2003 ,  H01L23/66 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1066 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/788 ,  H01L29/94

Abstract: A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.

公开(公告)号：US20170250274A1

公开(公告)日：2017-08-31

申请号：US15386746

申请日：2016-12-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/02694 ,  H01L21/2258 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/266 ,  H01L29/0688 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7783

Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

公开(公告)号：US20200161445A1

公开(公告)日：2020-05-21

申请号：US16597600

申请日：2019-10-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Koichi ARAI ,  Nobuo MACHIDA

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/36 ,  H01L29/417

Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20180219089A1

公开(公告)日：2018-08-02

申请号：US15841676

申请日：2017-12-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/66431 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789

Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

公开(公告)号：US20180026099A1

公开(公告)日：2018-01-25

申请号：US15604848

申请日：2017-05-25

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAMA ,  Atsushi TSUBOI ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/1087 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.

公开(公告)号：US20170162683A1

公开(公告)日：2017-06-08

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yoshinao MIURA ,  Takashi INOUE

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/205 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US20170047437A1

公开(公告)日：2017-02-16

申请号：US15216817

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L21/02 ,  H01L21/324 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/2258 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/808

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has an impurity-containing potential fixed layer, and a gate electrode. A drain electrode and a source electrode are formed on the opposite sides of the gate electrode. An interlayer insulation film is formed between the gate electrode and the drain electrode, and between the gate electrode and the source electrode. The concentration of the inactivating element in the portion of the potential fixed layer under the drain electrode is higher than the concentration of the inactivating element in the portion of the potential fixed layer under the source electrode. The film thickness of the portion of the interlayer insulation film between the gate electrode and the drain electrode is different from the film thickness of the portion of the interlayer insulation film between the gate electrode and the source electrode.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有含杂质的电位固定层和栅电极。 漏电极和源电极形成在栅电极的相对侧上。 在栅电极和漏电极之间以及栅电极和源电极之间形成层间绝缘膜。 在漏电极下方的电位固定层部分中的灭活元件的浓度高于源电极下的电位固定层部分中的钝化元件的浓度。 栅电极和漏电极之间的层间绝缘膜的部分的膜厚度与栅电极和源电极之间的层间绝缘膜的部分的膜厚不同。