公开(公告)号：US20180026099A1

公开(公告)日：2018-01-25

申请号：US15604848

申请日：2017-05-25

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAMA ,  Atsushi TSUBOI ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/1087 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.

公开(公告)号：US20170047437A1

公开(公告)日：2017-02-16

申请号：US15216817

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L21/02 ,  H01L21/324 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7783 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/2258 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/808

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has an impurity-containing potential fixed layer, and a gate electrode. A drain electrode and a source electrode are formed on the opposite sides of the gate electrode. An interlayer insulation film is formed between the gate electrode and the drain electrode, and between the gate electrode and the source electrode. The concentration of the inactivating element in the portion of the potential fixed layer under the drain electrode is higher than the concentration of the inactivating element in the portion of the potential fixed layer under the source electrode. The film thickness of the portion of the interlayer insulation film between the gate electrode and the drain electrode is different from the film thickness of the portion of the interlayer insulation film between the gate electrode and the source electrode.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有含杂质的电位固定层和栅电极。 漏电极和源电极形成在栅电极的相对侧上。 在栅电极和漏电极之间以及栅电极和源电极之间形成层间绝缘膜。 在漏电极下方的电位固定层部分中的灭活元件的浓度高于源电极下的电位固定层部分中的钝化元件的浓度。 栅电极和漏电极之间的层间绝缘膜的部分的膜厚度与栅电极和源电极之间的层间绝缘膜的部分的膜厚不同。

公开(公告)号：US20170170306A1

公开(公告)日：2017-06-15

申请号：US15361303

申请日：2016-11-25

Applicant: Renesas Electronics Corporation

Inventor： Tomoo NAKAYAMA ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7788 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.

公开(公告)号：US20160260615A1

公开(公告)日：2016-09-08

申请号：US14969053

申请日：2015-12-15

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro HIRAI ,  Hiroshi KAWAGUCHI

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L21/306 ,  H01L29/78 ,  H01L29/201 ,  H01L21/324 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L21/28114 ,  H01L21/3006 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: The present invention makes it possible to improve the characteristic of a semiconductor device using a nitride semiconductor. An electrically-conductive film is formed above a gate electrode above a substrate with an interlayer insulation film interposed and a source electrode coupled to a barrier layer on one side of the gate electrode and a drain electrode coupled to the barrier layer on the other side of the gate electrode are formed by etching the electrically-conductive film. On this occasion, the source electrode is etched so as to have a shape extending beyond above the gate electrode to the side of the drain electrode and having a gap (opening) above the gate electrode. Successively, hydrogen annealing is applied to the substrate. In this way, by forming the gap at a source field plate section of the source electrode, it is possible to efficiently supply hydrogen in the region where a channel is formed in the hydrogen annealing process.

Abstract translation: 本发明可以提高使用氮化物半导体的半导体器件的特性。 导电膜形成在衬底上方的栅电极之上，层间绝缘膜被插入，并且源电极耦合到栅电极一侧上的阻挡层，漏电极耦合到阻挡层的另一侧 通过蚀刻导电膜形成栅电极。 在这种情况下，源电极被蚀刻成具有延伸超过栅极电极到漏电极侧的形状，并且在栅电极上方具有间隙（开口）。 接着，将氢退火施加到基板上。 以这种方式，通过在源电极的源场极板部分形成间隙，可以在氢退火工艺中在形成沟道的区域中有效地提供氢。

公开(公告)号：US20160064538A1

公开(公告)日：2016-03-03

申请号：US14837053

申请日：2015-08-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/15 ,  H01L29/66 ,  H01L29/207 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有在衬底上形成的含有ap型杂质，沟道层和阻挡层的电位固定层，以及布置在穿过势垒层的沟槽中的栅极，并且通过沟道层的某一点通过 门绝缘膜。 源极和漏极形成在栅电极的相对侧上。 含p型杂质的电位固定层在栅电极和漏电极之间具有含有诸如氢之类的钝化元件的失活区域。 因此，在提高源电极侧的电位固定层的p型杂质（受体）浓度的同时，在漏电极侧使电位固定层的p型杂质失活。 这可以提高漏极侧击穿电压，同时通过p型杂质提供电荷的去除效果。

公开(公告)号：US20170288046A1

公开(公告)日：2017-10-05

申请号：US15463320

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI ,  Tatsuo NAKAYAMA

IPC: H01L29/778 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/30612 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7786

Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (θ1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

公开(公告)号：US20180061983A1

公开(公告)日：2018-03-01

申请号：US15789191

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170294538A1

公开(公告)日：2017-10-12

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.