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公开(公告)号：US20060179266A1
公开(公告)日：2006-08-10
申请号：US11054274
申请日：2005-02-09
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。
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公开(公告)号：US20060179258A1
公开(公告)日：2006-08-10
申请号：US11054262
申请日：2005-02-09
IPC分类号： G06F12/10
CPC分类号： G06F11/362
摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.
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3.发明申请Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品公开(公告)号：US20060184741A1
公开(公告)日：2006-08-17
申请号：US11055820
申请日：2005-02-11
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译： 在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。 动态分配缓存以在多个线程之间使用。 高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。 高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。 在执行线程期间，可以动态地更改部分的大小。
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4.发明申请Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中提取请求同时运行，而不管其一致等级公开(公告)号：US20060179227A1
公开(公告)日：2006-08-10
申请号：US11054293
申请日：2005-02-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译： 一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。 响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。 确定这些识别的未完成的有效提取条目使用的SetID。 所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。 用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。
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公开(公告)号：US20050122347A1
公开(公告)日：2005-06-09
申请号：US10728347
申请日：2003-12-04
申请人： Daniel Buerkle , David Hrusecky , Charles Marino , Chuck Ngai , John Urda
发明人： Daniel Buerkle , David Hrusecky , Charles Marino , Chuck Ngai , John Urda
CPC分类号： G06T3/40 , G06T1/60 , G09G2340/0407
摘要： An apparatus, circuit arrangement, program product and method of scaling an image horizontally partition a source image into a plurality of partitions, with each partition having a width that is no greater than the width of a line buffer used to scale the image. By partitioning an image into a plurality of partitions, the overall width of the scaled image is not constrained by the width of the line buffer. As a result, in many instances line buffers that are significantly smaller than conventional full-width line buffers may be used to generate scaled images that are substantially wider than may be generated by conventional buffers. Moreover, when implemented in hardware, the line buffers typically occupy significantly less real estate on an integrated circuit, thus reducing both cost and power consumption.
摘要翻译： 将图像缩放水平分割为多个分区的装置，电路装置，程序产品和方法，其中每个分区的宽度不大于用于缩放图像的行缓冲器的宽度。 通过将图像分割成多个分区，缩放图像的总宽度不受线路缓冲器的宽度的约束。 结果，在许多情况下，显着小于常规全宽线缓冲器的行缓冲器可以用于产生比可能由常规缓冲器产生的图像大得多的缩放图像。 此外，当以硬件实现时，线路缓冲器通常在集成电路上占据明显更少的空间，从而降低成本和功耗。
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