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公开(公告)号：US11030118B2
公开(公告)日：2021-06-08
申请号：US15849507
申请日：2017-12-20
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens , Sarvagya Kochak
IPC: G06F12/0862 , G06N20/00 , G06F12/14 , G06F3/06 , G06F21/79 , G06F21/57 , G06F9/4401
Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.
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公开(公告)号：US11615037B2
公开(公告)日：2023-03-28
申请号：US17306410
申请日：2021-05-03
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.
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公开(公告)号：US11042492B2
公开(公告)日：2021-06-22
申请号：US16631163
申请日：2018-10-17
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.
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公开(公告)号：US20230259466A1
公开(公告)日：2023-08-17
申请号：US18171817
申请日：2023-02-21
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
CPC classification number: G06F13/1668 , G06F13/4282 , G06F2213/0016
Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.
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公开(公告)号：US20200226079A1
公开(公告)日：2020-07-16
申请号：US16631163
申请日：2018-10-17
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.
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Patent Agency Ranking
公开(公告)号：US20210343318A1
公开(公告)日：2021-11-04
申请号：US17284433
申请日：2019-10-07
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
IPC: G11C7/10 , G11C7/22 , G11C11/4093
Abstract: A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode. The first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.
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公开(公告)号：US20210311888A1
公开(公告)日：2021-10-07
申请号：US17306410
申请日：2021-05-03
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.
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公开(公告)号：US20180260339A1
公开(公告)日：2018-09-13
申请号：US15849507
申请日：2017-12-20
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens , Sarvagya Kochak
CPC classification number: G06F12/1408 , G06F3/062 , G06F3/0623 , G06F3/0629 , G06F3/0658 , G06F3/0679 , G06F3/0685 , G06F9/4401 , G06F21/575 , G06F21/79 , G06F2212/1052
Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.
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公开(公告)号：US11886360B2
公开(公告)日：2024-01-30
申请号：US18171817
申请日：2023-02-21
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
CPC classification number: G06F13/1668 , G06F13/4282 , G06F2213/0016
Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.
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公开(公告)号：US11443784B2
公开(公告)日：2022-09-13
申请号：US17284433
申请日：2019-10-07
Applicant: Rambus Inc.
Inventor： Aws Shallal , Larry Grant Giddens
IPC: G11C7/10 , G11C7/22 , G11C11/4093
Abstract: A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode. The first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.
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