公开(公告)号：US12072817B2

公开(公告)日：2024-08-27

申请号：US18216439

申请日：2023-06-29

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US11734208B2

公开(公告)日：2023-08-22

申请号：US18082446

申请日：2022-12-15

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US11184198B2

公开(公告)日：2021-11-23

申请号：US16811353

申请日：2020-03-06

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

公开(公告)号：US10601615B2

公开(公告)日：2020-03-24

申请号：US16161547

申请日：2018-10-16

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

公开(公告)号：US10135642B2

公开(公告)日：2018-11-20

申请号：US15438571

申请日：2017-02-21

Applicant: Rambus Inc.

Inventor： Marko Aleksić ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H03H7/30 ,  H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

公开(公告)号：US09368164B2

公开(公告)日：2016-06-14

申请号：US14086818

申请日：2013-11-21

Applicant: RAMBUS INC.

Inventor： Pravin Kumar Venkatesan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar ,  Wayne Dettloff

IPC: G11C7/00 ,  G11C5/14 ,  G11C7/10 ,  G11C7/04 ,  G11C11/4099 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C29/023 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4076 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2207/2254 ,  H03M1/66

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract translation: 单端接收器包括用于设定第一内部参考电压（Vref）的内部电压产生电路。 模型电压发生电路可配置为在初始校准期间接收要校准的外部参考电压。 模型电压发生电路可配置为跟踪电压 - 温度（VT）漂移的偏移值，并且在单端接收器的周期性校准期间，将偏移值应用于内部电压产生电路以校准内部Vref。

公开(公告)号：US20190149366A1

公开(公告)日：2019-05-16

申请号：US16161547

申请日：2018-10-16

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H04L25/03 ,  H04L1/00 ,  H03M13/21 ,  H03M13/00

CPC classification number: H04L25/03057 ,  H03M13/21 ,  H03M13/6502 ,  H04L1/0047 ,  H04L1/0057

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

公开(公告)号：US10089256B2

公开(公告)日：2018-10-02

申请号：US15616785

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

IPC: G06F13/16

Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

公开(公告)号：US20170250840A1

公开(公告)日：2017-08-31

申请号：US15438571

申请日：2017-02-21

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H04L25/03 ,  H03M13/00 ,  H04L1/00 ,  H03M13/21

CPC classification number: H04L25/03057 ,  H03M13/21 ,  H03M13/6502 ,  H04L1/0047 ,  H04L1/0057

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

公开(公告)号：US09711239B2

公开(公告)日：2017-07-18

申请号：US15169156

申请日：2016-05-31

Applicant: RAMBUS INC.

Inventor： Pravin Kumar Venkatesan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar ,  Wayne Dettloff

IPC: G11C7/00 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14 ,  G11C7/04 ,  G11C11/4099 ,  G11C11/4076 ,  G11C29/52 ,  H03M1/66 ,  G11C29/04

CPC classification number: G11C29/023 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4076 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2207/2254 ,  H03M1/66

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.