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13 条记录 (耗时 0.019 秒)

    ESD protection device with reduced clamping voltage
    1.
    发明授权
    ESD protection device with reduced clamping voltage 有权
    降低钳位电压的ESD保护器件

    公开(公告)号：US08873210B2

    公开(公告)日：2014-10-28

    申请号：US13607959

    申请日：2012-09-10

    申请人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    发明人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    IPC分类号： H02H3/22 ,  H02H9/04 ,  H01L27/02

    CPC分类号： H01L27/0259 ,  H02H9/046

    摘要： Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

    摘要翻译： 公开了一种ESD保护电路，其包括多个双极晶体管，即在第一和第二端子（T1，T2）之间的主ESD导电路径中的多个ESD导电晶体管（Q1，Q2，Q4） 包括至少一个驱动晶体管（Q3），所述至少一个驱动晶体管（Q3）并联连接到所述ESD导电晶体管（Q1）中的至少一个，并被提供用于在发生时向一个或多个ESD导电晶体管（Q3）传导驱动电流（Ib2） 的ESD事件。

    ESD Protection Device With Reduced Clamping Voltage
    2.
    发明申请
    ESD Protection Device With Reduced Clamping Voltage 有权
    具有降低钳位电压的ESD保护器件

    公开(公告)号：US20130063846A1

    公开(公告)日：2013-03-14

    申请号：US13607959

    申请日：2012-09-10

    申请人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    发明人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0259 ,  H02H9/046

    摘要： Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

    摘要翻译： 公开了一种ESD保护电路，其包括多个双极晶体管，即在第一和第二端子（T1，T2）之间的主ESD导电路径中的多个ESD导电晶体管（Q1，Q2，Q4） 包括至少一个驱动晶体管（Q3），所述至少一个驱动晶体管（Q3）并联连接到所述ESD导电晶体管（Q1）中的至少一个，并被提供用于在发生时向一个或多个ESD导电晶体管（Q3）传导驱动电流（Ib2） 的ESD事件。

    A/D converter comprising a voltage comparator device
    3.
    发明授权
    A/D converter comprising a voltage comparator device 有权
    A / D转换器包括电压比较器装置

    公开(公告)号：US07652600B2

    公开(公告)日：2010-01-26

    申请号：US12191059

    申请日：2008-08-13

    申请人： Geert Van der Plas ,  Johan Bauwelinck ,  Zhisheng Li ,  Guy Torfs ,  Jan Vandewege ,  Xin Yin

    发明人： Geert Van der Plas ,  Johan Bauwelinck ,  Zhisheng Li ,  Guy Torfs ,  Jan Vandewege ,  Xin Yin

    IPC分类号： H03M1/10

    CPC分类号： H03M1/1061 ,  H03M1/0809 ,  H03M1/0863 ,  H03M1/361

    摘要： The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.

    摘要翻译： 本发明公开了一种包括至少两个电压比较器装置的模拟 - 数字转换器。 每个电压比较器装置包括晶体管的差分结构，并且被布置为被馈送相同的输入信号并且通过差分结构中的不平衡来产生自己的内部参考电压，所述两个内部电压基准是不同的。 每个电压比较器被布置用于产生指示输入信号的数字近似的位位置的输出信号。

    Circuit for end-of-burst detection
    6.
    发明授权
    Circuit for end-of-burst detection 有权
    脉冲串检测电路

    公开(公告)号：US08380079B2

    公开(公告)日：2013-02-19

    申请号：US12886298

    申请日：2010-09-20

    申请人： Cedric Mélange ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    发明人： Cedric Mélange ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    IPC分类号： H04B10/00 ,  H04B10/06

    CPC分类号： H04L7/042

    摘要： A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

    摘要翻译： 公开了一种用于在接收的比特流的一部分中进行爆发结束检测的电路。 该电路包括：第一计数器，用于对该部分中的比特数进行计数;第二计数器，用于对该部分中的比特值转换的数量进行计数;以及电路，用于比较该部分中计数的比特数和计数的 其中具有预设值的位值转换，用于比较的电路还被布置为基于比较的结果来产生指示爆发结束检测的信号。

    Systems and methods for transferring single-ended burst signal onto differential lines, especially for use in burst-mode receiver
    7.
    发明授权
    Systems and methods for transferring single-ended burst signal onto differential lines, especially for use in burst-mode receiver 有权
    将单端突发信号传输到差分线路上的系统和方法，特别适用于突发模式接收机

    公开(公告)号：US08150272B2

    公开(公告)日：2012-04-03

    申请号：US12089316

    申请日：2008-04-04

    申请人： Peter Ossieur ,  Tine De Ridder ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    发明人： Peter Ossieur ,  Tine De Ridder ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    IPC分类号： H04B10/06

    CPC分类号： H04B10/6931 ,  H04B10/272

    摘要： Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

    摘要翻译： 用于传送其输入的单端突发信号的系统和方法，其中至少一个特征从突发到突发到一对差分线之间广泛变化。 该系统包括用于接收输入突发信号的输入端，用于调整所述广泛变化的特性的信号调整块和单端到差分转换器。 在第一方面，优选地使用共模信号，通过差分线路向后发送用于复位控制信号适配块的设置确定块的复位信号。 在第二方面，采用状态冻结机制来冻结输入突发的前导码结束之后的设置确定块的设置。

    Systems and Methods for Transferring Single-Ended Burst Signal Onto Differential Lines, Especially for Use in Burst-Mode Receiver
    8.
    发明申请
    Systems and Methods for Transferring Single-Ended Burst Signal Onto Differential Lines, Especially for Use in Burst-Mode Receiver 有权
    将单端突发信号传输到差分线的系统和方法，特别用于突发模式接收机

    公开(公告)号：US20110311227A9

    公开(公告)日：2011-12-22

    申请号：US12089316

    申请日：2008-04-04

    申请人： Peter Ossieur ,  Tine De Ridder ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    发明人： Peter Ossieur ,  Tine De Ridder ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    IPC分类号： H04J14/00

    CPC分类号： H04B10/6931 ,  H04B10/272

    摘要： Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

    摘要翻译： 用于传送其输入的单端突发信号的系统和方法，其中至少一个特征从突发到突发到一对差分线之间广泛变化。 该系统包括用于接收输入突发信号的输入端，用于调整所述广泛变化的特性的信号调整块和单端到差分转换器。 在第一方面，优选地使用共模信号，通过差分线路向后发送用于复位控制信号适配块的设置确定块的复位信号。 在第二方面，采用状态冻结机制来冻结输入突发的前导码结束之后的设置确定块的设置。

    Circuit for End-of-Burst Detection
    10.
    发明申请
    Circuit for End-of-Burst Detection 有权
    电路用于突发检测

    公开(公告)号：US20110069952A1

    公开(公告)日：2011-03-24

    申请号：US12886298

    申请日：2010-09-20

    申请人： Cedric Mélange ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    发明人： Cedric Mélange ,  Johan Bauwelinck ,  Xing Zhi Qiu ,  Jan Vandewege

    IPC分类号： H04B10/08

    CPC分类号： H04L7/042

    摘要： A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

    摘要翻译： 公开了一种用于在接收的比特流的一部分中进行爆发结束检测的电路。 该电路包括：第一计数器，用于对该部分中的比特数进行计数;第二计数器，用于对该部分中的比特值转换的数量进行计数;以及电路，用于比较该部分中计数的比特数和计数的 其中具有预设值的位值转换，用于比较的电路还被布置为基于比较的结果来产生指示爆发结束检测的信号。