公开(公告)号：US20160293481A1

公开(公告)日：2016-10-06

申请号：US15068547

申请日：2016-03-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI ,  Keiji SAKAMOTO ,  Hiroyuki KUNISHIMA

IPC: H01L21/768 ,  G02B6/134 ,  G02B6/136 ,  G02F1/025 ,  H01L23/544 ,  G02B6/122

CPC classification number: G02B6/1347 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/121 ,  G02F1/025 ,  H01L23/562

Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.

Abstract translation: 在构成SOI晶片的绝缘膜上形成由半导体层形成的矩形光波导，光学移相器和光调制器，然后去除形成在SOI晶片的后表面上的后绝缘膜。 此外，在绝缘膜的平面图中看到，在与矩形光波导，光移相器和光调制器不重叠的位置处形成有从绝缘膜的上表面开始的第一深度的多个沟槽 。 结果，即使当SOI晶片后来安装在包括在半导体制造装置中的静电卡盘上时，也可以容易地从SOI晶片释放电荷，所以电荷不太可能积聚在半导体制造装置的背面 SOI晶圆。

公开(公告)号：US20180158816A1

公开(公告)日：2018-06-07

申请号：US15883289

申请日：2018-01-30

Applicant: Renesas Electronics Corporation

Inventor： Satoshi KURA ,  Mitsuo NISSA ,  Keiji SAKAMOTO ,  Taichi IWASAKI

IPC: H01L27/088 ,  H01L49/02 ,  H01L27/108 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/24

Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

公开(公告)号：US20170307824A1

公开(公告)日：2017-10-26

申请号：US15647838

申请日：2017-07-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI ,  Keiji SAKAMOTO ,  Hiroyuki KUNISHIMA

IPC: G02B6/134 ,  G02F1/025 ,  G02B6/122 ,  G02B6/12 ,  G02B6/136 ,  H01L23/00

CPC classification number: G02B6/1347 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/121 ,  G02F1/025 ,  H01L23/562

Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.

公开(公告)号：US20170069769A1

公开(公告)日：2017-03-09

申请号：US15244853

申请日：2016-08-23

Applicant: Renesas Electronics Corporation ,  Photonics Electronics Technology Research Association

Inventor： Tatsuya USAMI ,  Yoshiaki YAMAMOTO ,  Keiji SAKAMOTO ,  Tohru MOGAMI ,  Tsuyoshi HORIKAWA ,  Keizo KINOSHITA

IPC: H01L31/0232 ,  H01L31/18 ,  G02B6/136 ,  G02B6/12 ,  G02B6/122

CPC classification number: H01L31/02327 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L31/1808

Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，通过绝缘层在基体上形成由硅制成的第一半导体部分和第二半导体部分，并且在第二半导体上形成包括由锗制成的半导体层的第三半导体部分 一部分。 接着，在第一半导体部分的上方形成绝缘膜，形成从绝缘膜的上表面到达第一半导体部分的开口部，在第一半导体的上表面的一部分上形成金属硅化物层 部分暴露于开口部分。

公开(公告)号：US20160284980A1

公开(公告)日：2016-09-29

申请号：US15060820

申请日：2016-03-04

Applicant: Renesas Electronics Corporation

Inventor： Takashi TONEGAWA ,  Keiji SAKAMOTO

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.

Abstract translation: 本发明的目的是防止磁性隧道结中的短路故障，从而抑制具有磁存储单元的半导体器件的可靠性降低。 首先，对数据参考层和盖层进行图案化。 在其侧壁上形成无氧的第一绝缘膜之后，对基底层，数据记录层和隧道势垒层进行图案化。 在图案化基底层，数据记录层和隧道势垒层时，可以防止数据参考层和覆盖层与隧道势垒层的侧壁的粘附，因为数据参考层和盖 层被第一绝缘膜覆盖。