公开(公告)号：US20150042500A1

公开(公告)日：2015-02-12

申请号：US14336073

申请日：2014-07-21

Applicant: Renesas Electronics Corporation

Inventor： Masaki FUJIWARA ,  Yasuo MORIMOTO ,  Takashi MATSUMOTO

IPC: H03K3/86 ,  H03M1/38

CPC classification number: H03M1/125 ,  H03K5/133 ,  H03K2005/00065 ,  H03M1/12 ,  H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468

Abstract: To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Abstract translation: 提供能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号，该半导体器件检测当该周期从比较期间转变到该时间段时是否输出信号及其延迟信号 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

公开(公告)号：US20160094239A1

公开(公告)日：2016-03-31

申请号：US14848924

申请日：2015-09-09

Applicant: Renesas Electronics Corporation

Inventor： Masaki FUJIWARA ,  Yasuo MORIMOTO ,  Takashi MATSUMOTO

IPC: H03M1/12 ,  H03K5/13 ,  H03M1/46

CPC classification number: H03M1/125 ,  H03K5/133 ,  H03K2005/00065 ,  H03M1/12 ,  H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468

Abstract: A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Abstract translation: 能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号，该半导体器件检测当该周期从比较期间转变到该时间段时是否输出信号及其延迟信号 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

公开(公告)号：US20130265180A1

公开(公告)日：2013-10-10

申请号：US13794308

申请日：2013-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi MATSUMOTO ,  Masao ITO ,  Osamu MATSUMOTO ,  Hiroto SUZUKI

IPC: H03M1/46 ,  H03M1/38

CPC classification number: H03M1/38 ,  H03M1/0697 ,  H03M1/46

Abstract: A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.

Abstract translation: 在逐次逼近寄存器A / D转换器的操作基于集成电路中的电路定时受到影响的定时，获得N位输出的逐次逼近寄存器A / D转换器中断操作。 A / D转换器将采样信号和比较参考电压进行比较，其中采样模拟信号的采样周期，将采样信号顺序地与每个位的比较电压相比较的N个状态的比较周期 ，以及比较期间M州的储备期。 当操作暂时中断时，A / D转换器执行位的比较操作，而在保留期间不进行比较。